Abstract: The present invention provides architectures for hybrid integrated circuits and methods for producing these hybrid integrated circuits that contain both field programmable gate arrays and mask programmable gate arrays, a form of application specific integrated circuits. Methods for producing an integrated circuit that is field programmable as well as mask programmable include the steps of: designing wafer bank layers and finishing layers, where the wafer bank layers provide a plurality of selectable functional blocks; fabricating said wafer bank layers; designing mask programmed interconnect layers for said integrated circuit, where the interconnect layers interconnect selected ones of the plurality of functional blocks from the wafer bank layers; fabricating the interconnect layers on the wafer bank layers; and fabricating the finishing layers on the interconnect layers to produce the integrated circuit.

Abstract: A programmable interconnect network for an array of logic cells. Said interconnect network has a plurality of switch boxes being connected in a tree structure and providing connections to its logic cells, switch boxes located at the lowest level of the tree structure are connected to logic cells; said interconnect network also has peripheral switch boxes, of which at least one is connected to an external logic. Also, an integrated circuit comprising an FP array of logic cells connected by the said programmable interconnect network and a mask programmable (MP) logic array.

Abstract: A programmable interconnect network for an array of logic cells. Said interconnect network has a plurality of switch boxes being connected in a tree structure and providing connections to its logic cells, switch boxes located at the lowest level of the tree structure are connected to logic cells; said interconnect network also has peripheral switch boxes, of which at least one is connected to an external logic. Also, an integrated circuit comprising an FP array of logic cells connected by the said programmable interconnect network and a mask programmable (MP) logic array.

Abstract: The present invention provides architectures for hybrid integrated circuits and methods for producing these hybrid integrated circuits that contain both field programmable gate arrays and mask programmable gate arrays, a form of application specific integrated circuits. Methods for producing an integrated circuit that is field programmable as well as mask programmable include the steps of: designing wafer bank layers and finishing layers, where the wafer bank layers provide a plurality of selectable functional blocks; fabricating said wafer bank layers; designing mask programmed interconnect layers for said integrated circuit, where the interconnect layers interconnect selected ones of the plurality of functional blocks from the wafer bank layers; fabricating the interconnect layers on the wafer bank layers; and fabricating the finishing layers on the interconnect layers to produce the integrated circuit.