Patents by Inventor John K. Arledge
John K. Arledge has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7594318Abstract: A multilayer substrate assembly (80) includes at least one embedded component (52) within a plurality of stacked pre-processed substrates. Each pre-processed substrate can have a core dielectric (14), patterned conductive surfaces (12 and 16) on opposing sides of the core dielectric, and at least one hole (18) in each of at least two adjacently stacked pre-processed substrates such that at least two holes are substantially aligned on top of each other forming a single hole (19). The assembly further includes a processed adhesive layer (48) between top and bottom surfaces of respective pre-processed substrates. The embedded component is placed in the single hole and forms a gap (67 & 66) between the embedded component and a peripheral wall of the single hole. When the assembly is biased, the processed adhesive layer fills the gap to form the assembly having the embedded component cross-secting the plurality of pre-processed substrates.Type: GrantFiled: September 12, 2007Date of Patent: September 29, 2009Assignee: Motorola, Inc.Inventors: James A. Zollo, John K. Arledge, Nitin B. Desai
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Patent number: 7286366Abstract: A multilayer substrate assembly (80) includes at least one embedded component (52) within a plurality of stacked pre-processed substrates. Each pre-processed substrate can have a core dielectric (14), patterned conductive surfaces (12 and 16) on opposing sides of the core dielectric, and at least one hole (18) in each of at least two adjacently stacked pre-processed substrates such that at least two holes are substantially aligned on top of each other forming a single hole (19). The assembly further includes a processed adhesive layer (48) between top and bottom surfaces of respective pre-processed substrates. The embedded component is placed in the single hole and forms a gap (67 & 66) between the embedded component and a peripheral wall of the single hole. When the assembly is biased, the processed adhesive layer fills the gap to form the assembly having the embedded component cross-secting the plurality of pre-processed substrates.Type: GrantFiled: March 24, 2005Date of Patent: October 23, 2007Assignee: Motorola, Inc.Inventors: James A. Zollo, John K. Arledge, Nitin B. Desai
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Patent number: 7132357Abstract: A method for shielding one or more circuits (21, 21?) of a printed circuit board includes depositing a layer of dielectric material (43) over a printed circuit board substrate (22) and the printed circuits (21, 21?), creating a trench-like opening (44) in the dielectric layer (43) such that the trench-like opening (44) surrounds the one or more circuits (21, 21?) to be shielded, depositing a layer of metal (27) over the layer of dielectric material (43) and within the trench-like openings (44), creating a solder pad (24) at each location where an electrical connection is to be made to the printed circuits (21, 21?) by removing a border of the metal layer (27) surrounding each connection location, and providing a microvia (25) through each solder pad (24) penetrating the dielectric layer (43) and terminating at the metal of the printed circuit (21, 21?).Type: GrantFiled: September 29, 2005Date of Patent: November 7, 2006Assignee: Motorola, Inc.Inventors: Jeffrey A. Underwood, John K. Arledge, Thomas J. Swirbel, Joaquin Barreto
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Patent number: 6990734Abstract: Methods for forming a metal shield on a printed circuit board (10) include depositing a first layer of metal (41) on a substrate (22) of the printed circuit board (10), depositing a first layer of dielectric material (42) on the first layer of metal (41), printing one or more circuits (21, 21?) on the first dielectric layer (42), depositing a second layer of dielectric material (43) over the one or more printed circuits (21, 21?), forming a trench-like opening (44) in the two layers of dielectric material (42, 43) surrounding the one or more printed circuits (21, 21?) so that the metal of the first layer (41) is exposed by the trench-like opening (44), depositing a second layer of metal (27) on the second layer of dielectric material (43) such that the second layer of metal (27) plates the trench-like opening (44) and makes electrical contact with the first metal layer (41).Type: GrantFiled: October 2, 2002Date of Patent: January 31, 2006Assignee: Motorola, Inc.Inventors: Jeffrey A. Underwood, John K. Arledge, Thomas J. Swirbel, Joaquin Barreto
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Patent number: 6928726Abstract: A substrate assembly (10) and method of making same has at least one embedded component (25) in a via (24) of a substrate core (22) and includes a first adhesive layer (20) coupled to the substrate core, and a second adhesive layer (26) on at least portions of a top surface of the substrate core and above portions of the embedded component. The substrate assembly can further include a first conductive layer (18) adhered to the bottom surface of the substrate core and a second conductive layer (28) on the second adhesive layer. The substrate assembly can further include an interconnection (36) between a conductive surface of the embedded component and at least one among the first conductive layer and the second conductive layer. The interconnection can be formed through an opening (34) that at least temporarily exposes at least a conductive surface (32) of the embedded component.Type: GrantFiled: July 24, 2003Date of Patent: August 16, 2005Assignee: Motorola, Inc.Inventors: James A. Zollo, John K. Arledge, John C. Barron, Gary R. Burhance, John Holley, Henry F. Liebman
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Patent number: 6653915Abstract: A method of forming a coaxial transmission line on a high density PCB. A metal layer (102) on the PCB (104) forms the bottom part of the shield, and is covered by a first dielectric (112). Two parallel trenches (122) are formed in the first dielectric to reveal part (123) of the metal strip. The signal conductor (132) is then formed on the first dielectric. A second dielectric (142) covers the signal conductor and the first dielectric. A second set of two parallel trenches (172) are formed in the second dielectric immediately above the first two trenches. Metal deposit (182) is plated in the parallel trenches to contact the metal strip, and also covers a portion of the second dielectric that lies between the trenches, to create a shield. The resulting coaxial transmission line has a center conductor insulated from the shield by the dielectrics.Type: GrantFiled: August 20, 1999Date of Patent: November 25, 2003Assignee: Motorola, Inc.Inventors: John K. Arledge, Joaquin Barreto, Thomas J. Swirbel, Jeffrey A. Underwood
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Publication number: 20030024719Abstract: Methods and apparatus for forming a metal shield on a printed circuit board (10) include a layer of dielectric material (23) one or more printed circuits (21) on the layer of dielectric material (23), a layer of metal (27) on the layer of dielectric material (23), a metal-clad trench or opening surrounding the printed circuit (44) and electrically connected to the layer of metal(27), a solder pad (24) on the layer of dielectric material (23), a microvia (25) through the solder pad (24) and the layer of dielectric material (23), and electrical components (11) soldered to the solder pads (24) and to the printed circuit (21).Type: ApplicationFiled: October 2, 2002Publication date: February 6, 2003Applicant: Motorola, Inc.Inventors: Jeffrey A. Underwood, John K. Arledge, Thomas J. Swirbel, Joaquin Barreto
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Patent number: 6515222Abstract: Methods and apparatus for forming a metal shield on a printed circuit board (10) include a layer of dielectric material (23) one or more printed circuits (21) on the layer of dielectric material (23), a layer of metal (27) on the layer of dielectric material (23), a metal-clad trench or opening surrounding the printed circuit (44) and electrically connected to the layer of metal(27), a solder pad (24) on the layer of dielectric material (23), a microvia (25) through the solder pad (24) and the layer of dielectric material (23), and electrical components (11) soldered to the solder pads (24) and to the printed circuit (21).Type: GrantFiled: February 5, 2001Date of Patent: February 4, 2003Assignee: Motorola, Inc.Inventors: Jeffrey A. Underwood, John K. Arledge, Thomas J. Swirbel, Joaquin Barreto
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Patent number: 6493198Abstract: An electrostatic discharge protection device for a high-density printed circuit board consists of a layered structure starting at the bottom layer with a ground conductor. A dielectric layer covers the ground conductor to electrically isolate it from a circuit trace that is on top of the dielectric layer. A via is formed in the dielectric layer such that a portion of the ground conductor is exposed, and the via is strategically located such that the edge of the via is tangent to an edge portion of the circuit trace. The via forms a spark gap between the edge portion of the circuit trace and the underlying ground conductor, using air as the dielectric medium.Type: GrantFiled: February 22, 2000Date of Patent: December 10, 2002Assignee: Motorola, Inc.Inventors: John K. Arledge, Jeffrey A. Underwood, Joaquin Barreto
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Publication number: 20020104669Abstract: Methods and apparatus for forming a metal shield on a printed circuit board (10) include a layer of dielectric material (23) one or more printed circuits (21) on the layer of dielectric material (23), a layer of metal (27) on the layer of dielectric material (23), a metal-clad trench or opening surrounding the printed circuit (44) and electrically connected to the layer of metal (27), a solder pad (24) on the layer of dielectric material (23), a microvia (25) through the solder pad (24) and the layer of dielectric material (23), and electrical components (11) soldered to the solder pads (24) and to the printed circuit (21).Type: ApplicationFiled: February 5, 2001Publication date: August 8, 2002Inventors: Jeffrey A. Underwood, John K. Arledge, Thomas J. Swirbel, Joaquin Barreto
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Patent number: 6388202Abstract: A high density multi-layer printed circuit board (100) is formed by building additional dielectric and metallization layers over a central core (110) of conventional PCB laminate construction. The central core has a metallization pattern (113, 114) on at least one surface. A photoimaged dielectric layer (130) is deposited on one side of the central core and overlies the metallization pattern. Vias (136) are formed in this dielectric layer by a photoimaging process, and an additional metallization pattern (133) on this layer is electrically connected to the underlying metallization pattern through these vias. A non-photoimageable dielectric layer (120) is deposited on the other side of the central core. Vias (126) are formed in this dielectric layer by a laser drilling process, and an additional metallization pattern (123) on this layer is electrically connected to an underlying metallization pattern through these laser drilled vias.Type: GrantFiled: October 6, 1997Date of Patent: May 14, 2002Assignee: Motorola, Inc.Inventors: Thomas J. Swirbel, John K. Arledge, Joaquin Barreto
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Patent number: 6080501Abstract: A fuel cell (30) has an internal fuel source (35) that is in a matrix around a membrane electrode assembly (29). The membrane electrode assembly is constructed to be generally formed in the shape of a solid cylinder. The fuel cell has a porous central core (22) of reticulated vitreous metal that is formed in the shape of a solid cylinder. The porous central core serves to distribute oxidant throughout the fuel cell. A cathode (23) is situated coaxially around the porous central core, and has a catalytic layer on the outer side. A solid polymer electrolyte (25) is situated coaxially around the cathode and in intimate contact with the catalytic layer. An anode (27) is situated coaxially around the electrolyte, and a second layer of catalytic material is situated between the electrolyte and the anode. A housing (31) contains the internal fuel supply and holds the membrane electrode assemblies in place.Type: GrantFiled: June 29, 1998Date of Patent: June 27, 2000Assignee: Motorola, Inc.Inventors: Ronald J. Kelley, Steven D. Pratt, John K. Arledge, Sivakumar Muthuswamy, James L. Davis
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Patent number: 6000120Abstract: A method of forming a coaxial transmission line on a high density PCB. A metal strip (102) on the PCB (104) forms the bottom part of the shield, and is covered by a first dielectric (112). Two parallel trenches (122) are formed in the first dielectric to reveal part (123) of the metal strip. The signal conductor (132) is then formed on the first dielectric. A second dielectric (142) covers the signal conductor and the first dielectric. A second set of two parallel trenches (172) are formed in the second dielectric immediately above the first two trenches. Metal (182) is plated in the parallel trenches to contact the metal strip, and also covers a portion of the second dielectric that lies between the trenches, to create a shield. The resulting coaxial transmission line has a center conductor insulated from the shield by the dielectrics.Type: GrantFiled: April 16, 1998Date of Patent: December 14, 1999Assignee: Motorola, Inc.Inventors: John K. Arledge, Joaquin Barreto, Thomas J. Swirbel, Jeffrey A. Underwood
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Patent number: 5891795Abstract: A method of creating high density interlayer interconnects on circuit carrying substrates. A circuit pattern (20) is formed on one side of a substrate (10), and gold balls (30) are selectively placed on the circuit pattern using a thermosonic ball bonder. A liquid solution of a polymer is cast directly on the substrate and the etched circuit pattern such that only the upper portion of each gold ball is revealed when the liquid polymer solution is then dried and cured to form a dry film (40). A second layer of metal is then deposited directly on the dry film, such that it is electrically and mechanically connected to the exposed top of the gold balls. A second circuit pattern (50) is then formed in the second layer of metal. The resulting high density interconnect has two circuit layers separated by a dielectric layer. Each circuit layer is connected to the other by the gold balls that serve as conductive vias.Type: GrantFiled: March 18, 1996Date of Patent: April 6, 1999Assignee: Motorola, Inc.Inventors: John K. Arledge, Thomas J. Swirbel
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Patent number: 5869899Abstract: A method of creating high density interlayer interconnects on circuit carrying substrates. A circuit pattern (20) is formed on one side of a substrate (10), and gold balls (30) are selectively placed on the circuit pattern using a thermosonic ball bonder. A liquid solution of a polymer is cast directly on the substrate and the etched circuit pattern such that only the upper portion of each gold ball is revealed when the liquid polymer solution is then dried and cured to form a dry film (40). A second layer of metal is then deposited directly on the dry film, such that it is electrically and mechanically connected to the exposed top of the gold balls. A second circuit pattern (50) is then formed in the second layer of metal. The resulting high density interconnect has two circuit layers separated by a dielectric layer. Each circuit layer is connected to the other by the gold balls that serve as conductive vias.Type: GrantFiled: May 13, 1998Date of Patent: February 9, 1999Assignee: Motorola, Inc.Inventors: John K. Arledge, Thomas J. Swirbel
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Patent number: 5591480Abstract: One method for fabricating solderable pads (406) onto a substrate (220) for direct chip attachment uses a multilayer metallization coating (500). The coating has a bottom layer (202) of indium-tin oxide, with an intermediate layer (204) of copper and a top layer (206) of indium-tin oxide. A masking layer (208) is deposited on the active display area (402) of the substrate, leaving the bonding pads uncovered. The revealed bonding pads are then plasma etched, using the polyimide as an etch resist, and the top layer of ITO is selectively removed to reveal the underlying copper layer. The exposed copper layer (204) is then plated with a solderable metal to the desired thickness to form bonding pads that may be used with direct chip attachment schemes.Type: GrantFiled: August 21, 1995Date of Patent: January 7, 1997Assignee: Motorola, Inc.Inventors: Douglas H. Weisman, Thomas J. Swirbel, John K. Arledge
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Patent number: 5576052Abstract: A method of manufacturing high aspect ratio plated through holes in a circuit carrying substrate. High aspect ratio apertures or holes (16) are formed in a substrate (10). A thin film of copper (20) is sputtered onto the substrate and in the apertures that a macroscopically discontinuous copper film (26) is formed on part of the aperture walls. The macroscopically discontinuous copper film is substantially thinner than the copper film that is deposited on the surface. A catalytic copper coating (30) is plated directly on the vacuum deposited thin film of copper by electroless copper plating in a manner sufficient to form a macroscopically continuous copper layer on the aperture walls.Type: GrantFiled: April 22, 1996Date of Patent: November 19, 1996Assignee: Motorola, Inc.Inventors: John K. Arledge, Thomas J. Swirbel, Joaquin Barreto
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Patent number: 5529863Abstract: A method for fabricating solderable pads (106) onto a glass substrate (101) includes the step of depositing a seed metallization layer (step 406) after the polyimide layer is cured (step 404) but prior to buffing the alignment layer (step 414). The seed metallization layer can done by, for example, sputter depositing indium-tin, tin or copper.Type: GrantFiled: July 17, 1995Date of Patent: June 25, 1996Assignee: Motorola, Inc.Inventors: Thomas J. Swirbel, John K. Arledge
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Patent number: 5460922Abstract: A method of forming electrode patterns on a substrate. A substrate (30) is patterned with a photoresist layer (14) on the front side so that portions (18) of the substrate are revealed. A metal oxide layer (32) is deposited on the patterned photoresist layer and the revealed portions of the substrate. The patterned photoresist layer is then flood exposed to actinic radiation (19). The photoresist pattern (20) is removed, carrying with it those portions of the metal oxide layer deposited on the photoresist layer, forming an electrode pattern (22) by a lift-off technique.Type: GrantFiled: July 18, 1994Date of Patent: October 24, 1995Assignee: Motorola, Inc.Inventors: Thomas J. Swirbel, John K. Arledge, James L. Davis
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Patent number: 5437941Abstract: An electrical energy storage device (10). An electrode (12) consisting of a thin film of metal or metal oxide is deposited on a substrate (24), preferably by sputtering. Spherical plastic spacers (16) are uniformly dispersed on the electrode at a maximum density of about 1000 spacers per square millimeter of the electrode area. A second substrate also has an electrode (14) formed of a thin film of metal or metal oxide deposited on it, similar to the first substrate. The first and second substrates are arranged so that the electrodes face each other and are separated by the spherical plastic spacers to form a gap (18) of about 20 microns between the electrodes. An electrolyte (20) is filled in the gap, and the edges of the gap are optionally sealed (22) to form the electrical energy storage device. The device may also be formed by using metal foils, and eliminating one or more of the substrates. In both cases, the use of an electrolyte is optional.Type: GrantFiled: January 17, 1995Date of Patent: August 1, 1995Assignee: Motorola, Inc.Inventors: John K. Arledge, James L. Davis, Thomas J. Swirbel