Abstract: A cross-connect switch (12) uses a matrix (40) for providing connection paths. The matrix (40) includes prioritization logic (42) for receiving connection requests from restoration state machines (50) (for changing connections responsive to line conditions) and an administrative processor (for changing connections responsive to operator commands). Connection requests from both the restoration state machines (50) and the administrative processor (52) are cached in FIFO memories (54). When a FIFO memory (54) stores one or more connection requests, the switching control circuitry is notified by a data ready signal. Logic (56) inhibits passing of the data ready signal from the FIFO memory (54) to the switching control (26) until all restoration connection requests have been serviced.

Abstract: A cross-connect switch (12) uses a matrix (40) for providing connection paths. The matrix (40) includes prioritization logic (42) for receiving connection requests from restoration state machines (50) (for changing connections responsive to line conditions) and an administrative processor (for changing connections responsive to operator commands). Connection requests from both the restoration state machines (50) and the administrative processor (52) are cached in FIFO memories (54). When a FIFO memory (54) stores one or more connection requests, the switching control circuitry is notified by a data ready signal. Logic (56) inhibits passing of the data ready signal from the FIFO memory (54) to the switching control (26) until all restoration connection requests have been serviced.

Abstract: A digital circuit which ascertains the middle of a digital pulse by first determining its total length through digital logic means in combination with a digital signal delay means, and uses this information to operate a state machine (or sequencer), which will assume that data clocks occur at the time of the last received valid data pulse until new logic "1" data is received, and at this time can be resynchronized or phase-locked if there is a time discrepancy between recently received data and the status of the state machine.