Abstract: An image processing system incorporates a distortion correction (DC) sub-system in order to quickly correct skewed images. The DC sub-system includes a buffer, a processor and a sparse matrix table (SMT). The buffer is sized according to an amount of distortion in an input image. Input image pixels from an input frame are buffered in the buffer, and other input image pixels from the same frame overwrite the buffered input image pixels, reducing latency of the DC sub-system. The SMT is dynamically configurable and provides mapping values for mapping output pixels to input pixels. The processor implements combinational logic, including multipliers, lookup tables and adders. The combinational logic interpolates flow control parameters, pixel coordinate values, and pixel intensity values. The distortion correction values are streamed to a display or provided to a subsequent image processing block for further processing.

Abstract: A method includes receiving a stream of synthetic images from a synthetic vision system and receiving a stream of sensor images from at least one sensor. The method also includes performing, by a processing array including a plurality of parallel processing elements, one or more fusion operations on a particular synthetic image of the stream of the synthetic images and one or more particular sensor images of the stream of the sensor images. Upon performing one or more fusion operations on the particular synthetic image of the stream of the synthetic images and the one or more particular sensor images of the stream of sensor images, the method further includes outputting a combined image to a display for presentation to a user.

Abstract: A microcoded processor that uses microinstructions to reduce power consumption utilizing low power consumption registers to store most recently retrieved data from a high power consumption control store; a control store in combination with an indirect register file to provide the micro-orders necessary for operation of the microcoded processor without extending the size of the microinstruction; and a microcode driven single clock cycle control to turn off circuitry when not needed.

Abstract: A nested hierarchical plurality of microcoded compute engines where each successive compute engine is coupled to a source bus and a sink bus of another microcoded computed engine at a different hierarchical level, where one microcoded compute engine may be a replacement of a scratchpad memory or FIFO from a pre-existing design. A communication scheme for communicating between and within various hierarchical layers of microcoded compute engines and a piano roll of bitmapped barrier objects for synchronizing activities of various microcomputer engines.

Abstract: The present invention includes an image processing system with several data compression processing units connected together with a communication bus. Each data compression processing unit includes a wavelet transform processing unit, a shared register file and an address computation processing unit. The wavelet transform processing unit decomposes data from one or more segments of an image into wavelets using a discrete wavelet transform. The shared register stores the intermediate wavelet coefficient computations. The address computation processing unit identifies addresses of wavelets to be decomposed by subsequent operation of the wavelet transform processing unit. The system also includes storage where the resultant wavelet coefficients from each segment may be stored. The present invention also includes methods of compressing image data using multiple processors where each processor operates on a segment of the image data.

Abstract: An improved micro architectural approach for a network microprocessor has low power consumption, and employs two specialized processing cores, a MAC processing core and a network processor core. Each of these processing cores has facilities designed for a specific set of functions, to handle ISO layer 2 and layer 3 functionality in a packet switched Software Defined Radio mobile network.

Abstract: An improved micro architectural approach for a network microprocessor has low power consumption, and employs two specialized processing cores, a MAC processing core and a network processor core. Each of these processing cores has facilities designed for a specific set of functions, to handle ISO layer 2 and layer 3 functionality in a packet switched Software Defined Radio mobile network.

Abstract: An improved architectural approach for implementation of a microarchitecture for a low power, small footprint microcoded processor for use in packet switched networks in software defined radio MANeTs. A plurality of on-board CPU caches and a system of virtual memory allows the microprocessor to employ a much larger program size, up to 64k words or more, given the size and power footprint of the microprocessor.

Abstract: A network processor with a high performance in computing throughput, size and power density for use in applications such as Software Defined Radio (SDR) mesh topology. The network processor uses a core architecture comprised of a programmable microcoded sequencer to implement state management and control, a data manipulation subsystem controlled by fully decoded microinstructions. To save power, the core architecture employs a fully decoded microcoded control unit, multiplexer based register select/write logic, between 10000 to 20000 gates, a power consumption of less than 10 mW.

Abstract: The present invention is a method including: receiving an input key string; comparing the input key string with a stored key string; and granting access to a boundary scan chain when the input key string matches the stored key string, the boundary scan chain being at least one of: a Boundary Data Register of at least one Joint Test Action Group (JTAG)-compliant device; or, a plurality of communicatively coupled JTAG-compliant devices.

Abstract: Multiple Java Virtual Machines (JVMs) operate on a single direct execution JAVA processor with each JVM operating in a separate time slice called a partition. Each JVM has its own data and control structures and is assigned a fixed area of memory. Each partition is also allotted a fixed period of time in which to operate, and, at the end of the allotted time, a context switch is forced to another JVM operating in the next partition. The context switch does not transfer control directly from one JVM to another JVM. Instead, at the end of a partition time period control is switched from the currently operating JVM to a “master JVM” during a time period called an “interstice.” The master JVM handles system interrupts and housekeeping duties. At the end of the interstice time period, the master JVM starts a proxy thread associated with the next JVM to become operational. The proxy thread handles JVM-specific interrupts and checks the status of the associated JVM.

Abstract: An improved computer architecture and system advantageously combine the beneficial characteristics of a high level object oriented programming language with an optimized processor for efficient application to real time embedded computing problems. Additionally, an improved method for resolving symbolic references in code generated by compiling source code written in an object oriented programming language to the corresponding logical memory addresses stores look-up information with the object itself after the first encounter of a given symbolic reference, whereby the logical memory address information is available for subsequent encounters of the symbolic reference, and whereby no modification of the program instructions containing the symbolic reference is necessary. In a preferred embodiment, the Java™ programming language is used.