Abstract: Techniques for tamper detection of a memory module having non-volatile memory devices resident on a printed circuit board (PCB) by circuitry of a controller also resident on the PCB. Examples include determining resistance values of a character pattern sprayed on a side of a cover facing the non-volatile memory devices using conductive ink following first and second boots of the memory module and asserting a bit of a register to indicate tampering of the memory modules based on a comparison of the resistance values. Tamper policy actions may be initiated based on detection of tampering.

Abstract: Technologies disclosed herein provide mitigations against warm boot attacks on memory modules. For instance, in one embodiment, a non-volatile dual in-line memory module (NVDIMM) in a host computing system may detect a transition from a low-power state to a full-power state, receive a nonce value from a processor of the host computing system after the transition, verify the nonce value, and allow access to data stored on the NVDIMM based on successful verification of the nonce value. In another embodiment, an NVDIMM may be locked in response to detecting a transition from a high-power state to a low-power state in a host computing system. After a transition from the low-power state to the full-power state, the NVDIMM may obtain one or more passphrases, verify the one or more passphrases, and allow access to data stored on the NVDIMM based on successful verification of the one or more passphrases.

Abstract: Examples may include techniques for use of a latch to secure a device inserted in a host computing system. The latch including a housing having holes or ports and an active contacts pad to receive external communication or control links routed through the holes or ports and to further route the communication or control links to circuitry at the device. The latch also including a securing pin attached to a lever to secure the device to the host computing system when the lever is engaged.

Abstract: Techniques for tamper detection of a memory module having non-volatile memory devices resident on a printed circuit board (PCB) by circuitry of a controller also resident on the PCB. Examples include determining resistance values of a character pattern sprayed on a side of a cover facing the non-volatile memory devices using conductive ink following first and second boots of the memory module and asserting a bit of a register to indicate tampering of the memory modules based on a comparison of the resistance values. Tamper policy actions may be initiated based on detection of tampering.

Abstract: Examples may include techniques for use of a latch to secure a device inserted in a host computing system. The latch including a housing having holes or ports and an active contacts pad to receive external communication or control links routed through the holes or ports and to further route the communication or control links to circuitry at the device. The latch also including a securing pin attached to a lever to secure the device to the host computing system when the lever is engaged.

Abstract: Technologies disclosed herein provide mitigations against warm boot attacks on memory modules. For instance, in one embodiment, a non-volatile dual in-line memory module (NVDIMM) in a host computing system may detect a transition from a low-power state to a full-power state, receive a nonce value from a processor of the host computing system after the transition, verify the nonce value, and allow access to data stored on the NVDIMM based on successful verification of the nonce value. In another embodiment, an NVDIMM may be locked in response to detecting a transition from a high-power state to a low-power state in a host computing system. After a transition from the low-power state to the full-power state, the NVDIMM may obtain one or more passphrases, verify the one or more passphrases, and allow access to data stored on the NVDIMM based on successful verification of the one or more passphrases.

Abstract: Methods and apparatus related to supporting both DDR (Double Data Rate) and NVM (Non-Volatile Memory) DIMM (Dual Inline Memory Module) on the same memory slot are described. In one embodiment, a DIMM comprises volatile memory and non-volatile memory, and data is communicated with the volatile memory and the non-volatile memory via a single memory slot. Other embodiments are also disclosed and claimed.

Abstract: Methods and apparatus related to supporting both DDR (Double Data Rate) and NVM (Non-Volatile Memory) DIMM (Dual Inline Memory Module) on the same memory slot are described. In one embodiment, a DIMM comprises volatile memory and non-volatile memory, and data is communicated with the volatile memory and the non-volatile memory via a single memory slot. Other embodiments are also disclosed and claimed.

Abstract: Memory modules, controllers, and electronic devices comprising memory modules are described. In one embodiment, a memory module comprises a nonvolatile memory and an interface to a volatile memory bus, at least one input power rail to receive power from a host platform, and a controller comprising logic, at least partially including hardware logic, to convert the power from the input power rail from an input voltage to at least one output voltage, different from the input voltage. Other embodiments are also disclosed and claimed.

Abstract: A memory system having volatile storage of data destined for secondary storage and smaller intermediate non-volatile storage of some of the data. The volatile memory is an array of DRAM storage devices integrated with the non-volatile memory array of SRAM devices by a mapping logic unit. The DRAM array stores all the data blocks destined for secondary storage. In contrast, the smaller SRAM array stores only the data requiring safe storage, which typically is a subset of the data stored in the DRAM array. The mapping logic unit manages the use of the SRAM array.

Abstract: Methodology and circuitry for managing read and write commands from nodes to a shared memory resource on a common data bus, including nodes with write-back caches, nodes with write-through caches and nodes without caches.

Abstract: A method and apparatus for implementing a capture of a long contiguous chain of data bus cycles for the memory system of a data processing system with memory units that alternate between real time capture of segments of the chain of data bus cycles and processing of the data bus signals in the captured segments.