Abstract: Disclosed is a linear feedback shift register (LFSR)-based clock signal generator that includes an LFSR, which outputs multi-bit states based on a system clock signal (CLK0). Based on the multi-bit states, a single-phase pulse generator generates first and second clock signals (CLK1 and CLK2), where the pulse rate of CLK1 is slower than that of the CLK0 and greater than that of CLK2. In some embodiments, a first multi-phase pulse generator can generate N-phases of the CLK1 based on CLK1 and N-phases of the CLK0 and a second multi-phase pulse generator can generate N-phases of CLK2 based on CLK2 and N-phases of CLK0. Furthermore, additional registers can optionally use the N-phases of CLK2 to further generate N sets of M-phases of the CLK2. Also disclosed are a multi-level circuit (e.g., a time domain-interleaved analog-to-digital converter (ADC)), which incorporates the LFSR-based clock signal generator, and associated methods.

Abstract: Aligning FIFO pointers includes resetting, by a write control block coupled to a write side of the FIFO, write pointers to an initial value. Then, iteratively, until one or more bits retrieved from the write side match one or more bits of an alignment bit pattern: providing, by the write side to the read side, the alignment bit pattern; retrieving, by the read side, one or more bits from the write side; providing, by the read side through a read control block, the retrieved one or more bits to the write control block; determining, by the write control block, whether the retrieved one or more bits match one or more bits of the alignment bit pattern; and, if the retrieved one or more bits do not match one or more bits of the alignment bit pattern, suppressing the read pointer from incrementing for a predetermined period of time.

Abstract: Aligning FIFO pointers includes resetting, by a write control block coupled to a write side of the FIFO, write pointers to an initial value. Then, iteratively, until one or more bits retrieved from the write side match one or more bits of an alignment bit pattern: providing, by the write side to the read side, the alignment bit pattern; retrieving, by the read side, one or more bits from the write side; providing, by the read side through a read control block, the retrieved one or more bits to the write control block; determining, by the write control block, whether the retrieved one or more bits match one or more bits of the alignment bit pattern; and, if the retrieved one or more bits do not match one or more bits of the alignment bit pattern, suppressing the read pointer from incrementing for a predetermined period of time.