Abstract: A comparator circuit (31) for sensing a voltage difference between a battery voltage and a power supply voltage is coupled to a switch (39). The comparator circuit is capable of accurately sensing a voltage near the power supply voltage. The comparator circuit (31) comprises a first amplification stage (32-36), a second amplification stage (37), and a Schmitt trigger (38). The first amplification stage (32-36) includes a first source follower (32) and a second source follower (33) for generating a differential voltage corresponding to a difference voltage between the battery voltage and the power supply voltage. The first amplification stage (32-36) reduces problems in amplifying voltage near the power supply voltage by level shifting the voltage through the use of source followers and insuring transistors operate in a saturation region of operation. The second amplification stage (37) further amplifies the difference voltage between the battery voltage and the power supply voltage.

Abstract: A storage cell circuit (11) comprises a voltage reduction circuit (17), a latch (18), and a tri-state driver circuit (19). The latch (18) has a terminal (14) and a terminal (16) for providing data stored therein. The voltage reduction circuit (17) couples to the power terminal of the latch (18) and reduces the voltage powering the latch. The tri-state driver circuit (19) has a clock input (12), a data input (13), a terminal coupled to the terminal (14), and a terminal coupled to the terminal (16). A clock signal applied to the clock input (12) has a first phase and a second phase. During the first phase of the clock, the terminals of the tri-state driver circuit (19) are at a high impedance leaving the data stored in the latch (18) undisturbed. During the second phase of the clock, the tri-state driver circuit (19) provides complementary signals of a data signal applied to the data input (13) for writing to the latch (18).

Abstract: An amplifier circuit receives biasing during power-up to reduce propagation delay. A start-up circuit generates first and second control signals upon detecting the power supply potential to the amplifier below a predetermined threshold. The control signals enable a biasing circuit to establish a bias potential at the input of the amplifier. After the power supply potential reaches the predetermined threshold, the control signals from the start-up circuit change state to disable the biasing circuit and allow the amplifier to operate normally.

Abstract: A frequency-controllable amplifier circuit is responsive to a frequency sensor for controlling the transconductance of an amplifier by adjusting the power supply potential thereof. The frequency sensor monitors the output frequency of the amplifier and generates a control signal having a first state upon detecting the output frequency above a predetermined threshold. The first state of the control signal increases the power supply potential to the amplifier which increase its transconductance. The frequency sensor also detects when the output frequency of the amplifier is below the predetermined threshold and switches the control signal to a second state to decrease the power supply potential to the amplifier which reduces its amplification.

Abstract: A crystal oscillator uses automatic gain control to minimize the operating current through its inverting amplifier. The power supply potential to switching transistors of the amplifier is reduced by the automatic gain control to a level substantially equal to the sum of the switching thresholds thereof which minimizes simultaneous conduction through the switching transistors and associated operating current. The low level output signal of the amplifier becomes sinusoidal about a DC bias point operating at the resonant frequency of the crystal which eliminates undesirable harmonicas interfering with the crystal's natural vibration. The sinusoidal output signal may be buffered and level-shifted to a useable state.

Abstract: A single-ended amplifier circuit is provided combining high speed operation with low input offset characteristics while providing immunity from power supply noise for the input signal by isolating the power supply conductors from the input conductor. The first and second amplifying transistors are separated from the power supply conductors by the drain-source conduction paths of third and fourth isolation transistors operating in their linear region in response to a predetermined reference potential. Thus, any power supply noise is absorbed across the third and fourth isolation transistors thereby avoiding overwhelming a low level input signal with switching induced noise.

Abstract: A circuit for providing a plurality of output functions at respective outputs by detecting the presence of an unusual voltage applied at its input thereof, comprising input circuit coupled to the input for transferring the input signal to a first output when the input signal is within a predetermined voltage range. A detection circuit coupled to the input for providing a detection signal at an output thereof when the input signal level exceeds a predetermined level in a predetermined sense. A buffer stage coupled between the output of the detection circuit and a second output, responsive to the detection signal, for providing a first binary logic state of the second output.

Abstract: A flipflop circuit is responsive to a clock signal for latching the terminal logic state of the input signal at an output irrespective of the relative transistions of the input data signal and the clock signal thereby providing immunity from the meta-stable condition. The input data signal is propagated from the input through a first stage to an intermediate node during a first clock cycle. A boost signal is applied at the intermediate node via first or second transistors for driving the potential developed thereat toward the terminal logic state of the input data signal. The logic state stored at the intermediate node may be used as the output signal or passed through additional buffer stages to an output during subsequent cycles of the clock signal.

Abstract: A power-on reset circuit includes a start-up voltage generator circuit which produces a voltage which is insensitive to changes in the threshold voltages of the field effect transistors contained therein. The start-up voltage then controls a trigger voltage for sheering a current to a capacitor, the current being provided by a switchable current source. The capacitor charges, therein introducing a delay into the generation of the reset signal. The reset signal is fedback to the start-up voltage generator circuit to reduce the steady state current drawn by the power-on reset circuit. A test terminal is provided to force the reset signal to go low for in circuit testing. This also provides a means for resetting internal memory elements which may be couple to the output of the power-on reset circuit to a known state.

Abstract: A power-on reset circuit includes a trigger voltage generating circuit which, when activated, causes current from a current source to be steered so as to charge a capacitor. When the voltage on the capacitor reaches a predetermined value, a switchable output stage is switched so as to generate the desired power-on reset signal. The trigger voltage generating circuit is responsive to a threshold voltage which tracks the power supply voltage and which is generated by separate circuitry.

Abstract: A switchable current source is provided for providing a relatively high frequency pulsed current to a load. The current source comprises six MOS transistors responsive to an enable signal and an input comprising a pulsating digital signal provide a pulsating digital output signal substantially similar to the input signal.

Abstract: A one shot circuit having feedback from the output to an input gate is provided to inhibit the input gate when an output is being provided. This feedback inhibits the input gate thereby preventing noise on the input from falsely triggering the one shot. A capacitor in conjunction with a Schmitt trigger is used to determine output pulse width. The output pulse width can be increased by adding additional capacitance to the first capacitor which is fully integrated on an integrated circuit chip. A reset input is also provided so that the circuit can be reset upon command.

Abstract: A power sensing circuit and method responsive to applied circuit voltages such that subsequent circuitry will be immediately powered down when the applied voltage drops below a specified level and generating a predetermined delay for powering up the subsequent circuitry when the applied voltage rises back to the same specified level.