Patents by Inventor John K. Skrovan

John K. Skrovan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7276765
    Abstract: A buried transistor particularly suitable for SOI technology, where the transistor is fabricated within a trench in a substrate and the resulting transistor incorporates completely isolated active areas. The resulting substrate has a decreased topography and there is no need for polysilicon (or other) plugs to connect to the transistor, unless desired. With this invention, better control is achieved in processing, particularly of gate length. The substrate having the buried transistor can be silicon oxide bonded to another substrate to form an SOI structure.
    Type: Grant
    Filed: March 21, 2005
    Date of Patent: October 2, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Theodore M. Taylor, Won-Joo Kim, John K. Skrovan
  • Patent number: 6900500
    Abstract: A buried transistor particularly suitable for SOI technology, where the transistor is fabricated within a trench in a substrate and the resulting transistor incorporates completely isolated active areas. The resulting substrate has a decreased topography and there is no need for polysilicon (or other) plugs to connect to the transistor, unless desired. With this invention, better control is achieved in processing, particularly of gate length. The substrate having the buried transistor can be silicon oxide bonded to another substrate to form an SOI structure.
    Type: Grant
    Filed: August 21, 2002
    Date of Patent: May 31, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Theodore M. Taylor, Won-Joo Kim, John K. Skrovan
  • Publication number: 20040036114
    Abstract: A buried transistor particularly suitable for SOI technology, where the transistor is fabricated within a trench in a substrate and the resulting transistor incorporates completely isolated active areas. The resulting substrate has a decreased topography and there is no need for polysilicon (or other) plugs to connect to the transistor, unless desired. With this invention, better control is achieved in processing, particularly of gate length. The substrate having the buried transistor can be silicon oxide bonded to another substrate to form an SOI structure.
    Type: Application
    Filed: August 21, 2002
    Publication date: February 26, 2004
    Inventors: Theodore M. Taylor, Won-Joo Kim, John K. Skrovan
  • Patent number: 6309282
    Abstract: An abrasive polishing pad for planarizing a substrate. In one embodiment, the abrasive polishing pad has a planarizing surface with a first planarizing region and a second planarizing region. The first planarizing region has a first abrasiveness and the second planarizing region has a second abrasiveness different than the first abrasiveness of the first region. The polishing pad preferably has a plurality of abrasive elements at the planarizing surface in at least one of the first or second planarizing regions. The abrasive elements may be abrasive particles fixedly suspended in a suspension medium, contact/non-contact regions on the pad, or other elements that mechanically remove material from the wafer.
    Type: Grant
    Filed: September 8, 2000
    Date of Patent: October 30, 2001
    Assignee: Micron Technology, Inc.
    Inventors: David Q. Wright, John K. Skrovan
  • Patent number: 6186870
    Abstract: An abrasive polishing pad for planarizing a substrate. In one embodiment, the abrasive polishing pad has a planarizing surface with a first planarizing region and a second planarizing region. The first planarizing region has a first abrasiveness and the second planarizing region has a second abrasiveness different than the first abrasiveness of the first region. The polishing pad preferably has a plurality of abrasive elements at the planarizing surface in at least one of the first or second planarizing regions. The abrasive elements may be abrasive particles fixedly suspended in a suspension medium, contact/non-contact regions on the pad, or other elements that mechanically remove material from the wafer.
    Type: Grant
    Filed: August 19, 1999
    Date of Patent: February 13, 2001
    Assignee: Micron Technology, Inc.
    Inventors: David Q. Wright, John K. Skrovan
  • Patent number: 6136043
    Abstract: The present invention is directed to polishing pads useful in determining an end to the useful wear life thereof. In a simple embodiment of the present invention, a polishing pad that is used with slurries is dyed on one side in a manner that causes the dye to permeate the pad to a limited depth that does not cause total coloring. Another embodiment of the present invention involves a fixed abrasive pad that has fixed abrasives embedded into the pad to a selected depth where at least one color level is within the portion of the pad that contains the fixed abrasives. After dyeing the pad, the pad is attached to the polishing platen. During the polishing operation, a color change signals a time to stop the polishing operation and change the pad. With multiple colors in the pad, limited only by the ability to dye the pad with uniform depth levels, characteristic wear patterns can be observed and adjustments made accordingly to prolong and optimize pad life.
    Type: Grant
    Filed: April 20, 1999
    Date of Patent: October 24, 2000
    Assignee: Micron Technology, Inc.
    Inventors: Karl M. Robinson, Michael A. Walker, John K. Skrovan
  • Patent number: 6090475
    Abstract: The present invention is directed to polishing pads useful in determining an end to the useful wear life thereof. In a simple embodiment of the present invention, a polishing pad that is used with slurries is dyed on one side in a manner that causes the dye to permeate the pad to a limited depth that does not cause total coloring. Another embodiment of the present invention involves a fixed abrasive pad that has fixed abrasives embedded into the pad to a selected depth where at least one color level is within the portion of the pad that contains the fixed abrasives. After dyeing the pad, the pad is attached to the polishing platen. During the polishing operation, a color change signals a time to stop the polishing operation and change the pad. With multiple colors in the pad, limited only by the ability to dye the pad with uniform depth levels, characteristic wear patterns can be observed and adjustments made accordingly to prolong and optimize pad life.
    Type: Grant
    Filed: April 4, 1997
    Date of Patent: July 18, 2000
    Assignee: Micron Technology Inc.
    Inventors: Karl M. Robinson, Michael A. Walker, John K. Skrovan
  • Patent number: 6062958
    Abstract: An abrasive polishing pad for planarizing a substrate. In one embodiment, the abrasive polishing pad has a planarizing surface with a first planarizing region and a second planarizing region. The first planarizing region has a first abrasiveness and the second planarizing region has a second abrasiveness different than the first abrasiveness of the first region. The polishing pad preferably has a plurality of abrasive elements at the planarizing surface in at least one of the first or second planarizing regions. The abrasive elements may be abrasive particles fixedly suspended in a suspension medium, contact/non-contact regions on the pad, or other elements that mechanically remove material from the wafer.
    Type: Grant
    Filed: April 4, 1997
    Date of Patent: May 16, 2000
    Assignee: Micron Technology, Inc.
    Inventors: David Q. Wright, John K. Skrovan