Abstract: A transfer request bus and transfer request bus node is described which is suitable for use in a data transfer controller processing multiple concurrent transfer requests despite the attendant collisions which result when conflicting transfer requests occur. Transfer requests are passed from an upstream transfer request node to downstream transfer request node and then to a transfer request controller with queue. At each node a local transfer request can also be inserted to be passed on to the transfer controller queue. Collisions at each transfer request node are resolved using a token passing scheme wherein a transfer request node possessing the token allows a local request to be inserted in preference to the upstream request.

Abstract: A data processing apparatus includes first (78) and second (80) functional unit groups, each includes a plurality of functional units and a register file (76) comprising a plurality of registers. A comparator (181) receives the operand register number of a current instruction for a functional unit in the first functional unit group, and the destination register number of an immediately preceding instruction for the second functional unit group. A register file bypass multiplexer (174) selects the data from the register corresponding to the operand number of the current instruction on no match and selects the output of the second functional unit group (hotpath 172) if the comparator indicates a match. The first functional unit utilizes the output of the second functional unit group without waiting for the result to be stored in the register file.

Abstract: A data processing apparatus and method for quickly and efficiently producing a diagonally (170) mirrored image of a block of data (168). The apparatus comprises a first input operand (182) consisting of a first half of an N×N bit data block and a second input operand (184) consisting of a second half of an N×N bit data block. A first hardware bit transformation (188) forms an upper half of an N-way bit deal of the two operands (186), and a second hardware bit transformation (192) forms a lower half of the N-way bit deal (190). The upper and lower halves of the N-way bit deal represent a diagonally mirrored image (172) of the N×N bit data block. The method retrieves a data block from memory and packs it into two input operand registers. The two hardware bit transformations fill respective destination registers. The data is unpacked from the destination registers and stored to memory.

Abstract: Data transfer between a master node (300) and plural memory nodes (301-308) follows a synchronous fixed latency loop bus (255). Each memory node includes bus interface (311-318) which passes command, write data, address and read data to a next memory node in the loop. Each memory node performs a read from its memory at the specified address if a read command is directed to it. Each memory node performs a write to its memory at the specified address if a write command is directed to it. This configuration provides a fixed latency between the issue of a read command and the return of the read data no matter which memory node is accessed. This configuration prevents collision of returning read data. This configuration retains the issued read and write order preserving proper function for read/write and write/read command pairs. This configuration provides fixed loading to each stage regardless of the number of memory nodes. Thus the design of large systems operating at high speeds is simplified.

Abstract: A transfer request bus (25) is described which is suitable for use in a data transfer controller processing, multiple concurrent transfer requests despite the attendant collisions which result when conflicting transfer requests occur. Transfer requests are passed from an upstream transfer request node (318) to downstream transfer request node (300) and thence to a transfer request controller with queue (320). At each node a local transfer request can also be inserted to be passed on to the transfer controller queue. Collisions at each transfer request node are resolved using a token passing scheme wherein a transfer request node possessing the token allows a local request to be inserted in preference to the upstream request.

Abstract: A data processing apparatus and method for quickly and efficiently producing a diagonally (170) mirrored image of a block of data (168). The apparatus comprises a first input operand (182) consisting of a first half of an N×N bit data block and a second input operand (184) consisting of a second half of an N×N bit data block. A first hardware bit transformation (188) forms an upper half of an N-way bit deal of the two operands (186), and a second hardware bit transformation (192) forms a lower half of the N-way bit deal (190). The upper and lower halves of the N-way bit deal represent a diagonally mirrored image (172) of the N×N bit data block. The method retrieves a data block from memory and packs it into two input operand registers. The two hardware bit transformations fill respective destination registers. The data is unpacked from the destination registers and stored to memory.

Abstract: A data processing apparatus for increasing the speed of data transfer from one processor instruction to another processor instruction. First (78) and second (80) functional unit groups, each including a plurality of functional units, are connected to a register file (76) comprising a plurality of registers having corresponding register numbers. A comparator (181) receives an indication of the operand register number of a current instruction for a functional unit in the first functional unit group, and an indication of the destination register number of an immediately preceding instruction for the second functional unit group, and indicates whether the register numbers match.

Abstract: Data transfer between multiple processor nodes and multiple static memory storage nodes is made more efficient using a wrapper of logic surrounding a conventional single port static memory function. The wrapper logic comprises FIFO devices which provide buffering between a given processor node and its associated memory function. The added buffering allows the design to trade allowable added read and write latency for a significant reduction in memory complexity. A single port random access memory structure enclosed within the wrapper provides the functional throughput advantage that only a dual port memory device would otherwise make possible.