Patents by Inventor John Kelley

John Kelley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11957273
    Abstract: A system for automatically folding a box for fast food delivery is disclosed. The system includes a wall, a track within the wall, a conveyer channel located adjacent to the wall. The panels are initially arranged within the channel, so a first panel is positioned above and in front of the second panel. The panels will move in a series of five positions. The first position having the first panel and second panel adjacent to one another. The second position shifting the second panel downward to a height lower than the first. The third position moving the first panel so that it is substantially vertical creating an angle near 90 degrees between the first and second panel. The fourth position returning the first panel proximate to its original position. And a fifth position having a portion of the first panel extended over the second panel.
    Type: Grant
    Filed: July 1, 2022
    Date of Patent: April 16, 2024
    Inventors: Dan Braido, Audley Wilson, John Kelley
  • Patent number: 11928060
    Abstract: A processing system includes a plurality of compute units, with each compute unit having an associated first cache of a plurality of first caches, and a second cache shared by the plurality of compute units. The second cache operates to manage transfers of caches between the first caches of the plurality of first caches such that when multiple candidate first caches contain a valid copy of a requested cacheline, the second cache selects the candidate first cache having the shortest total path from the second cache to the candidate first cache and from the candidate first cache to the compute unit issuing a request for the requested cacheline.
    Type: Grant
    Filed: February 8, 2022
    Date of Patent: March 12, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Sriram Srinivasan, John Kelley, Matthew Schoenwald
  • Patent number: 11880310
    Abstract: A processor includes a cache having two or more test regions and a larger non-test region. The processor further includes a cache controller that applies different cache replacement policies to the different test regions of the cache, and a performance monitor that measures performance metrics for the different test regions, such as a cache hit rate at each test region. Based on the performance metrics, the cache controller selects a cache replacement policy for the non-test region, such as selecting the replacement policy associated with the test region having the better performance metrics among the different test regions. The processor deskews the memory access measurements in response to a difference in the amount of accesses to the different test regions exceeding a threshold.
    Type: Grant
    Filed: December 16, 2021
    Date of Patent: January 23, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Paul Moyer, John Kelley
  • Patent number: 11868221
    Abstract: Techniques for performing cache operations are provided. The techniques include tracking performance events for a plurality of test sets of a cache, detecting a replacement policy change trigger event associated with a test set of the plurality of test sets, and in response to the replacement policy change trigger event, operating non-test sets of the cache according to a replacement policy associated with the test set.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: January 9, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventors: John Kelley, Vanchinathan Venkataramani, Paul J. Moyer
  • Patent number: 11803473
    Abstract: Systems and techniques for dynamic selection of policy that determines whether copies of shared cache lines in a processor core complex are to be stored and maintained in a level 3 (L3) cache of the processor core complex are based on one or more cache line sharing parameters or based on a counter that tracks L3 cache misses and cache-to-cache (C2C) transfers in the processor core complex, according to various embodiments. Shared cache lines are shared between processor cores or between threads. By comparing either the cache line sharing parameters or the counter to corresponding thresholds, a policy is set which defines whether copies of shared cache lines at such indices are to be retained in the L3 cache.
    Type: Grant
    Filed: November 8, 2021
    Date of Patent: October 31, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventors: John Kelley, Paul Moyer
  • Patent number: 11762646
    Abstract: Techniques are described for securely updating a point-of-sale (POS) system that includes a merchant-facing device and a buyer-facing device. For instance, the merchant-facing device may execute first software that provides first POS functionality and the buyer-facing device may execute second software that provides second POS functionality. To update both devices, the merchant-facing device may receive a software update from a payment service via a network connection, and update the first software using the software update. The merchant-facing device can then cause, via a physical connection, the buyer-facing device to reboot in an update mode and send the software update to the buyer-facing device. In response, the buyer-facing device can update the second software using the software update and then reboot in a payments mode. In some instances, the buyer-facing device can then update a secure enclave on the buyer-facing device using the software update.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: September 19, 2023
    Assignee: Block, Inc.
    Inventors: John Kelley, Max Guise, Todor Ristov, Imran Khan, Eric Monti
  • Publication number: 20230289290
    Abstract: A method includes monitoring one or more metrics for each of a plurality of cache users sharing a cache, and assigning each of the plurality of cache users to one of a plurality of groups based on the monitored one or more metrics.
    Type: Application
    Filed: May 17, 2023
    Publication date: September 14, 2023
    Applicant: Advanced Micro Devices, Inc.
    Inventor: John Kelley
  • Publication number: 20230274603
    Abstract: A method of vending an assembled food item. Receiving a request for an assembled food item. Conveying a first food item to a heating element for heating the first food item. Conveying a second food item to a second heating element for heating the second food item. Heating the first food item and second to a predetermined temperature or for an amount of time. After heating the first food item, dispensing the first food item into a first side of a foldable box that is open and dispensing the second food item into a second side of the foldable box. Folding the first side of the foldable box to be positioned substantially above the second side of the foldable box such that the foldable box is in a substantially closed position and such that the first food item is positioned substantially on top of the second food item.
    Type: Application
    Filed: April 12, 2023
    Publication date: August 31, 2023
    Inventors: Daniel Braido, Audley Wilson, John Kelley
  • Patent number: 11693778
    Abstract: A method includes monitoring one or more metrics for each of a plurality of cache users sharing a cache, and assigning each of the plurality of cache users to one of a plurality of groups based on the monitored one or more metrics.
    Type: Grant
    Filed: December 11, 2020
    Date of Patent: July 4, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventor: John Kelley
  • Publication number: 20230143760
    Abstract: Systems and techniques for dynamic selection of policy that determines whether copies of shared cache lines in a processor core complex are to be stored and maintained in a level 3 (L3) cache of the processor core complex are based on one or more cache line sharing parameters or based on a counter that tracks L3 cache misses and cache-to-cache (C2C) transfers in the processor core complex, according to various embodiments. Shared cache lines are shared between processor cores or between threads. By comparing either the cache line sharing parameters or the counter to corresponding thresholds, a policy is set which defines whether copies of shared cache lines at such indices are to be retained in the L3 cache.
    Type: Application
    Filed: November 8, 2021
    Publication date: May 11, 2023
    Inventors: John Kelley, Paul Moyer
  • Publication number: 20230109344
    Abstract: Techniques for performing cache operations are provided. The techniques include tracking performance events for a plurality of test sets of a cache, detecting a replacement policy change trigger event associated with a test set of the plurality of test sets, and in response to the replacement policy change trigger event, operating non-test sets of the cache according to a replacement policy associated with the test set.
    Type: Application
    Filed: September 30, 2021
    Publication date: April 6, 2023
    Applicant: Advanced Micro Devices, Inc.
    Inventors: John Kelley, Vanchinathan Venkataramani, Paul J. Moyer
  • Patent number: 11601741
    Abstract: Improved monaural headsets are provided. In some embodiments, a monaural headset includes: a first earphone with a speaker to provide output audio to a user; a second earphone without a speaker to provide output audio to the user; and a headband, connected to the first earphone and the second earphone; wherein the second earphone includes at least one vent opening, which vent opening during use provides an acoustic path between an environment of the user, wearing the headset, and the user's ear.
    Type: Grant
    Filed: October 21, 2021
    Date of Patent: March 7, 2023
    Assignee: PLANTRONICS, INC.
    Inventors: Jacob T. Meyberg Guzman, John Kelley, Darrin Caddes
  • Publication number: 20230069788
    Abstract: A system for automatically folding a box for fast food delivery is disclosed. The system includes a wall, a track within the wall, a conveyer channel located adjacent to the wall. The panels are initially arranged within the channel, so a first panel is positioned above and in front of the second panel. The panels will move in a series of five positions. The first position having the first panel and second panel adjacent to one another. The second position shifting the second panel downward to a height lower than the first. The third position moving the first panel so that it is substantially vertical creating an angle near 90 degrees between the first and second panel. The fourth position returning the first panel proximate to its original position. And a fifth position having a portion of the first panel extended over the second panel.
    Type: Application
    Filed: July 1, 2022
    Publication date: March 2, 2023
    Inventors: Dan Braido, Audley Wilson, John Kelley
  • Patent number: 11555632
    Abstract: The systems and methods disclosed relate to an air intake assembly, wherein the air intake assembly comprises: a frame comprising a plurality of openings, wherein each one of the plurality of openings comprises a V-shaped cross-section. The air intake assembly further comprises a plurality of slats, wherein each one of the plurality of slats comprises a V-shaped cross-section. The air intake assembly further comprises a stiffener configured to provide structural support to the plurality of slats, wherein the stiffener is disposed within an interior of the frame. The plurality of slats are disposed within the frame through the plurality of openings of the frame and through the stiffener.
    Type: Grant
    Filed: June 8, 2021
    Date of Patent: January 17, 2023
    Assignee: Toshiba International Corporation
    Inventors: John Kelley, Enrique Martinez
  • Patent number: 11483209
    Abstract: A communication network includes: a plurality of nodes in a topology, with each node having an upstream and a downstream neighboring node in the topology; a separate unidirectional communication link coupled between each node and that node's downstream neighboring node; and a separate unidirectional control link coupled between each node and that node's upstream neighboring node. A controller in each node keeps a count of packets sent by that node via the corresponding unidirectional communication link. The controller uses the count of packets sent to determine whether a given packet is allowed to be sent from that node to the downstream neighboring node and, if so, whether a full rate or a throttled rate is to be used for sending the given packet. Based at least in part on the determining, the controller selectively sends the given packet to the downstream neighboring node.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: October 25, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventors: John Kelley, Kartik Shenoy
  • Patent number: 11467937
    Abstract: An electronic device includes a cache with a cache controller and a cache memory. The electronic device also includes a cache policy manager. The cache policy manager causes the cache controller to use two or more cache policies for cache operations in each of multiple test regions in the cache memory, with different configuration values for the two or more cache policies being used in each test region. The cache policy manager selects a selected configuration value for at least one cache policy of the two or more cache policies based on performance metrics for cache operations while using the different configuration values for the two or more cache policies in the test regions. The cache policy manager causes the cache controller to use the selected configuration value when using the at least one cache policy for cache operations in a main region of the cache memory.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: October 11, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventors: John Kelley, Paul Moyer
  • Publication number: 20220188229
    Abstract: A method includes monitoring one or more metrics for each of a plurality of cache users sharing a cache, and assigning each of the plurality of cache users to one of a plurality of groups based on the monitored one or more metrics.
    Type: Application
    Filed: December 11, 2020
    Publication date: June 16, 2022
    Inventor: John Kelley
  • Patent number: 11275688
    Abstract: A processing system includes a plurality of compute units, with each compute unit having an associated first cache of a plurality of first caches, and a second cache shared by the plurality of compute units. The second cache operates to manage transfers of caches between the first caches of the plurality of first caches such that when multiple candidate first caches contain a valid copy of a requested cacheline, the second cache selects the candidate first cache having the shortest total path from the second cache to the candidate first cache and from the candidate first cache to the compute unit issuing a request for the requested cacheline.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: March 15, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Sriram Srinivasan, John Kelley, Matthew Schoenwald
  • Publication number: 20210406145
    Abstract: An electronic device includes a cache with a cache controller and a cache memory. The electronic device also includes a cache policy manager. The cache policy manager causes the cache controller to use two or more cache policies for cache operations in each of multiple test regions in the cache memory, with different configuration values for the two or more cache policies being used in each test region. The cache policy manager selects a selected configuration value for at least one cache policy of the two or more cache policies based on performance metrics for cache operations while using the different configuration values for the two or more cache policies in the test regions. The cache policy manager causes the cache controller to use the selected configuration value when using the at least one cache policy for cache operations in a main region of the cache memory.
    Type: Application
    Filed: August 27, 2020
    Publication date: December 30, 2021
    Inventors: John Kelley, Paul Moyer
  • Patent number: 11210234
    Abstract: A processor includes a cache having two or more test regions and a larger non-test region. The processor further includes a cache controller that applies different cache replacement policies to the different test regions of the cache, and a performance monitor that measures performance metrics for the different test regions, such as a cache hit rate at each test region. Based on the performance metrics, the cache controller selects a cache replacement policy for the non-test region, such as selecting the replacement policy associated with the test region having the better performance metrics among the different test regions. The processor deskews the memory access measurements in response to a difference in the amount of accesses to the different test regions exceeding a threshold.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: December 28, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Paul Moyer, John Kelley