Patents by Inventor John Kenneth DeBrosse
John Kenneth DeBrosse has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230049812Abstract: A spin-orbit torque magnetoresistive random-access memory device formed by forming an array of transistors, where a column of the array includes a source line contacting the source contact of each transistor of the column, forming a spin-orbit-torque (SOT) line contacting the drain contacts of the transistors of the row, and forming an array of unit cells, each unit cell including a spin-orbit-torque (SOT) magnetoresistive random access memory (MRAM) cell stack disposed above and in electrical contact with the SOT line, where the SOT-MRAM cell stack includes a free layer, a tunnel junction layer, and a reference layer, a diode structure above and in electrical contact with the SOT-MRAM cell stack, an upper electrode disposed above and in electrical contact with the diode structure.Type: ApplicationFiled: August 13, 2021Publication date: February 16, 2023Inventors: Daniel Worledge, Pouya Hashemi, John Kenneth DeBrosse
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Patent number: 11037645Abstract: Memory devices incorporating selective boosting techniques and methods for managing memory devices incorporating selective boosting techniques. One or more bit cells of a memory device are tested during a test phase and one or more addresses of one or more weak bit cells are stored in a non-volatile weak bit address memory within the memory device.Type: GrantFiled: June 25, 2019Date of Patent: June 15, 2021Assignee: International Business Machines CorporationInventors: Kotb Jabeur, John Kenneth DeBrosse
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Publication number: 20200411128Abstract: Memory devices incorporating selective boosting techniques and methods for managing memory devices incorporating selective boosting techniques. One or more bit cells of a memory device are tested during a test phase and one or more addresses of one or more weak bit cells are stored in a non-volatile weak bit address memory within the memory device.Type: ApplicationFiled: June 25, 2019Publication date: December 31, 2020Inventors: Kotb Jabeur, John Kenneth DeBrosse
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Patent number: 10741232Abstract: A memory device comprising a memory array of a plurality of memory bit cells; a read reference system comprising four or more reference memory bit cells in a reference column of the memory array; wherein a first bit cell of the reference memory bit cells is always selected; wherein a bitline of the first bit cell of the reference memory bit cells is connected to a bitline of a first subset of the reference memory bit cells, and a select line of the first bit cell of the reference memory bit cells is connected to a reference select signal; wherein a select line of each of the first subset of the reference memory bit cells and a second subset of the reference memory bit cells are coupled together; and wherein a bitline blref of the second subset of the reference memory bit cells outputs a read reference signal.Type: GrantFiled: June 25, 2019Date of Patent: August 11, 2020Assignee: International Business Machines CorporationInventors: Kotb Jabeur, John Kenneth DeBrosse
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Patent number: 10726897Abstract: A magnetoresistive random access memory (MRAM) system is described. The system includes a sense amplifier circuit for sensing a data state of an MRAM data cell. The circuit includes a first leg and a second leg, and is configured to perform a two-phase read including a first phase in which a first transistor is coupled to a reference resistance circuitry and a second transistor is coupled to a data resistance circuitry, and a second phase in which the first transistor is coupled to the data resistance circuitry and the second transistor is coupled to the reference resistance circuitry. The circuit further includes a reference trim circuitry and a data trim circuitry configured to correct for device mismatch errors relating to the two-phase read of the sense amplifier circuit. The circuit further includes a comparator circuit configured to output the data state of the data cell.Type: GrantFiled: May 14, 2019Date of Patent: July 28, 2020Assignee: International Business Machines CorporationInventors: Thomas Martin Maffitt, John Kenneth Debrosse, Matthew R Wordeman
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Patent number: 7376006Abstract: A nonvolatile memory cell includes a bipolar programmable storage element operative to store a logic state of the memory cell, and a metal-oxide-semiconductor device including first and second source/drains and a gate. A first terminal of the bipolar programmable storage element is adapted for connection to a first bit line. The first source/drain is connected to a second terminal of the bipolar programmable storage element, the second source/drain is adapted for connection to a second bit line, and the gate is adapted for connection to a word line.Type: GrantFiled: August 31, 2005Date of Patent: May 20, 2008Assignee: International Business Machines CorporationInventors: Johannes Georg Bednorz, John Kenneth DeBrosse, Chung Hon Lam, Gerhard Ingmar Meijer, Jonathan Zanhong Sun
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Patent number: 7192787Abstract: MRAMs are provided with cells offering low current leakage for partially selected cells. MRAM cells are made with magnetic tunnel junctions having barriers that meet predetermined low barrier heights and predetermined thicknesses. The barrier heights are preferably about 1.5 eV or less. The predetermined thicknesses are calculated to meet power and speed requirements. The predetermined low barrier heights and predetermined thicknesses modify a nonlinear term relating current through to voltage across the magnetic tunnel junction. The modification of the nonlinear term also modifies the amount of current that flows through a magnetic tunnel junction at various voltages. At low voltages, current through the magnetic tunnel junction will be disproportionately lower than current through a conventional magnetic tunnel junction. This decreases leakage current through partially selected MRAM cells and power.Type: GrantFiled: December 10, 2002Date of Patent: March 20, 2007Assignee: International Business Machines CorporationInventors: John Kenneth DeBrosse, Yu Lu, Stuart Stephen Papworth Parkin
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Patent number: 6946882Abstract: A symmetrical high-speed current sense amplifier having complementary reference cells and configurable load devices that eliminates architecture-related capacitive mismatch contributions. The current sense amplifier is adapted for use in a symmetric sensing architecture and includes a configurable load device. The current sense amplifier includes a voltage comparator, a first clamping device coupled between a first input of the voltage comparator and a first input signal, the first clamping device being coupled to a reference voltage. A second clamping device is coupled between the second input of the voltage comparator and a second input signal, the second clamping device being coupled to the reference voltage. The load device may comprise a current mirror that is coupled between the first and second input of the voltage comparator. The current mirror may be configurable by select transistors.Type: GrantFiled: December 20, 2002Date of Patent: September 20, 2005Assignees: Infineon Technologies AG, International Business Machines CorporationInventors: Dietmar Gogl, William Robert Reohr, John Kenneth DeBrosse
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Patent number: 6944049Abstract: A memory device includes a magnetic tunnel junction memory cell having a magnetic tunnel junction structure and a read switch. In one example, the read switch is connected to a conductor that is used to write to the magnetic tunnel junction structure. In a further example, the read switch is a transistor electrically coupled to the magnetic tunnel junction structure by a deep via contact. In a further example, the memory device includes a plurality of magnetic tunnel junction memory cells and a plurality of conductors respectively associated with the cells for writing information to the associated magnetic tunnel junction structures. Each read switch is connected to the conductor associated with a magnetic tunnel junction cell other than the cell in which the read switch resides.Type: GrantFiled: April 24, 2003Date of Patent: September 13, 2005Assignees: Infineon Technologies AG, International Business Machines CorporationInventors: Heinz Hoenigschmid, Dietmar Gogl, John Kenneth DeBrosse
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Patent number: 6930915Abstract: A method of storing information in a cross-point magnetic memory array and a cross-point magnetic memory device structure. The voltage drop across magnetic tunnel junctions (MTJ's) during a write operation is minimized to prevent damage to the MTJ's of the array. The voltage drop across the selected MTJ's, the unselected MTJ's, or both, is minimized during a write operation, reducing stress across the MTJ's, decreasing leakage currents, decreasing power consumption and increasing the write margin.Type: GrantFiled: June 19, 2003Date of Patent: August 16, 2005Assignees: Infineon Technologies AG, International Business Machines CorporationInventors: Stefan Lammers, Hans-Heinrich Viehmann, John Kenneth DeBrosse
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Publication number: 20040257869Abstract: A method of storing information in a cross-point magnetic memory array and a cross-point magnetic memory device structure. The voltage drop across magnetic tunnel junctions (MTJ's) during a write operation is minimized to prevent damage to the MTJ's of the array. The voltage drop across the selected MTJ's, the unselected MTJ's, or both, is minimized during a write operation, reducing stress across the MTJ'S, decreasing leakage currents, decreasing power consumption and increasing the write margin.Type: ApplicationFiled: June 19, 2003Publication date: December 23, 2004Inventors: Stefan Lammers, Hans-Heinrich Viehmann, John Kenneth DeBrosse
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Publication number: 20040120200Abstract: A symmetrical high-speed current sense amplifier having complementary reference cells and configurable load devices that eliminates architecture-related capacitive mismatch contributions. The current sense amplifier is adapted for use in a symmetric sensing architecture and includes a configurable load device. The current sense amplifier includes a voltage comparator, a first clamping device coupled between a first input of the voltage comparator and a first input signal, the first clamping device being coupled to a reference voltage. A second clamping device is coupled between the second input of the voltage comparator and a second input signal the second clamping device being coupled to the reference voltage. The load device may comprise a current mirror that is coupled between the first and second input of the voltage comparator. The current mirror may be configurable by select transistors.Type: ApplicationFiled: December 20, 2002Publication date: June 24, 2004Inventors: Dietmar Gogl, William Robert Reohr, John Kenneth DeBrosse
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Publication number: 20040109347Abstract: MRAMs are provided with cells offering low current leakage for partially selected cells. MRAM cells are made with magnetic tunnel junctions having barriers that meet predetermined low barrier heights and predetermined thicknesses. The barrier heights are preferably about 1.5 eV or less. The predetermined thicknesses are calculated to meet power and speed requirements. The predetermined low barrier heights and predetermined thicknesses modify a nonlinear term relating current through to voltage across the magnetic tunnel junction. The modification of the nonlinear term also modifies the amount of current that flows through a magnetic tunnel junction at various voltages. At low voltages, current through the magnetic tunnel junction will be disproportionately lower than current through a conventional magnetic tunnel junction. This decreases leakage current through partially selected MRAM cells and power.Type: ApplicationFiled: December 10, 2002Publication date: June 10, 2004Applicant: International Business Machines CorporationInventors: John Kenneth DeBrosse, Yu Lu, Stuart Stephen Papworth Parkin
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Publication number: 20040085810Abstract: A memory device includes a magnetic tunnel junction memory cell having a magnetic tunnel junction structure and a read switch. In one example, the read switch is connected to a conductor that is used to write to the magnetic tunnel junction structure. In a further example, the read switch is a transistor electrically coupled to the magnetic tunnel junction structure by a deep via contact. In a further example, the memory device includes a plurality of magnetic tunnel junction memory cells and a plurality of conductors respectively associated with the cells for writing information to the associated magnetic tunnel junction structures. Each read switch is connected to the conductor associated with a magnetic tunnel junction cell other than the cell in which the read switch resides.Type: ApplicationFiled: April 24, 2003Publication date: May 6, 2004Inventors: Heinz Hoenigschmid, Dietmar Gogl, John Kenneth DeBrosse
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Patent number: 6490217Abstract: A magnetic memory device for selectively writing one or more memory cells in the memory device includes a plurality of global write lines for selectively conveying a destabilizing current, the global write lines being disposed from the memory cells such that the destabilizing current passing through the global write lines does not destabilize unselected memory cells in the memory device, each global write line including a plurality of segmented write lines operatively connected thereto. The memory device further includes a plurality of segmented groups, each segmented group including a plurality of memory cells operatively coupled to a corresponding segmented write line, each segmented write line being disposed in relation to the plurality of corresponding memory cells such that the destabilizing current passing through the segmented write line destabilizes the corresponding memory cells for writing.Type: GrantFiled: May 23, 2001Date of Patent: December 3, 2002Assignee: International Business Machines CorporationInventors: John Kenneth DeBrosse, William Robert Reohr
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Publication number: 20020176272Abstract: A magnetic memory device for selectively writing one or more memory cells in the memory device includes a plurality of global write lines for selectively conveying a destabilizing current, the global write lines being disposed from the memory cells such that the destabilizing current passing through the global write lines does not destabilize unselected memory cells in the memory device, each global write line including a plurality of segmented write lines operatively connected thereto. The memory device further includes a plurality of segmented groups, each segmented group including a plurality of memory cells operatively coupled to a corresponding segmented write line, each segmented write line being disposed in relation to the plurality of corresponding memory cells such that the destabilizing current passing through the segmented write line destabilizes the corresponding memory cells for writing.Type: ApplicationFiled: May 23, 2001Publication date: November 28, 2002Applicant: International Business Machines CorporationInventors: John Kenneth DeBrosse, William Robert Reohr
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Patent number: 5804853Abstract: A semiconductor structure having electrical conductors positioned over each other, but electrically isolated from each other, is disclosed. The lower conductor has a recess in its upper surface, and the recess is at least partially filled with an oxide-type material, thereby isolating the lower conductor from the upper conductor. These conductors would normally contact each other because of the somewhat imprecise patterning and etching steps used to fabricate a multitude of conductive elements, e.g., in a very dense semiconductor structure. Stacked capacitor cells incorporating this structure are also disclosed.Type: GrantFiled: July 26, 1996Date of Patent: September 8, 1998Assignee: International Business Machines CorporationInventors: John Edward Cronin, John Kenneth DeBrosse, Hing Wong