Abstract: A structure and method operable to provide ESD protection for protected circuitry of automatic test equipment (ATE). In a disable mode, the first voltage potential and second voltage potential are substantially equivalent to the reference potential resulting in a clamping circuit providing a nominal clamping voltage to the protected circuit so that an ESD event having a voltage between the first voltage potential and the second voltage potential is shunted to the reference potential via first and second ESD rails, wherein the ESD event is received on a DUT node coupled to the one or more signal rails of the protected circuitry.