Abstract: An approach is provided that sends a JIT compilation request from a first process that is running on one processor to a JIT compiler that is running on another processor. The processors are based on different instruction set architectures (ISAs), and share a common memory to transfer data. Non-compiled statements are stored in the shared memory. The JIT compiler reads the non-compiled statements and compiles the statements into executable statements and stores them in the shared memory. The JIT compiler compiles the non-compiled statements destined for the first processor into executable instructions suitable for the first processor and statements destined for another type of processor (based on a different ISA) into instructions suitable for the other processor.

Abstract: An approach for managing position independent code using a software framework is presented. A software framework provides the ability to cache multiple plug-in's which are loaded in a processor's local storage. A processor receives a command or data stream from another processor, which includes information corresponding to a particular plug-in. The processor uses the plug-in identifier to load the plug-in from shared memory into local memory before it is required in order to minimize latency. When the data stream requests the processor to use the plug-in, the processor retrieves a location offset corresponding to the plug-in and applies the plug-in to the data stream. A plug-in manager manages an entry point table that identifies memory locations corresponding to each plug-in and, therefore, plug-ins may be placed anywhere in a processor's local memory.

Abstract: An approach is provided for vectorizing misaligned references in compiled code for SIMD architectures that support only aligned loads and stores. In the framework presented herein, a loop is first simdized as if the memory unit imposes no alignment constraints. The compiler then inserts data reorganization operations to satisfy the actual alignment requirement of the hardware. Finally, the code generation algorithm generates SIMD codes based on the data reorganization graph, addressing realistic issues such as runtime alignments, unknown loop bounds, residue iteration counts, and multiple statements with arbitrary alignment combinations. Beyond generating a valid simdization, a preferred embodiment further improves the quality of the generated codes. Four stream-shift placement policies are disclosed, which minimize the number of data reorganization generated by the alignment handling.

Abstract: A process, compiler, computer program product and system for workload partitioning in a heterogeneous system. The process includes determining heterogeneous alignment constraints in the workload, partitioning a portion of tasks to a processing element sensitive to alignment constraints, and partitioning a remaining portion of tasks to a processing element not sensitive to alignment constraints.

Abstract: A computer implemented method, apparatus, and computer usable program code for eliminating redundant read-modify-write code sequences in non-vectorizable code. Code is received comprising a sequence of operations. The sequence of operations includes a loop. Non-vectorizable operations are identified within the loop that modifies at least one sub-part of a storage location. The non-vectorizable operations are modified to include a single store operation for the number of sub-parts of the storage location.

Abstract: A system and method to efficiently pre-fetch and batch compiler-assisted software cache accesses are provided. The system and method reduce the overhead associated with software cache directory accesses. With the system and method, the local memory address of the cache line that stores the pre-fetched data is itself cached, such as in a register or well known location in local memory, so that a later data access does not need to perform address translation and software cache operations and can instead access the data directly from the software cache using the cached local memory address. This saves processor cycles that would otherwise be required to perform the address translation a second time when the data is to be used. Moreover, the system and method directly enable software cache accesses to be effectively decoupled from address translation in order to increase the overlap between computation and communication.

Abstract: A system and method for dividing an application into a number of logical program partitions is presented. Each of these logical program partitions are stored in a logical program package along with a execution monitor. The execution monitor runs in one of the processing environments of a heterogeneous processing environment. The logical program partition includes sets of object code for executing on each of the types of processors included in the heterogeneous processing environment. The logical program partition includes instrumentation data used to evaluate the performance of a currently executing partition. The execution monitor compares the instrumentation data to the gathered profile data. If the execution monitor determines that the partition is performing poorly then the code for the other environment is retrieved from the logical program package and loaded and executed on the other environment.

Abstract: A computer implemented method, data processing system, and computer usable program code are provided for configuring a cache. A compiler performs an analysis of software code to identify cacheable information in the software code that will be accessed in the cache at runtime. The properties of the cacheable information are analyzed to form a data reference analysis. Using the data reference analysis, a cache configuration is determined for caching the cacheable information during execution of the software code. Modified lookup code is inserted in the software code based on the cache configuration used to configure the cache.

Abstract: A system, method, and program product that sends a JIT compilation request from a first process that is running on one processor to a JIT compiler that is running on another processor is presented. The processors are based on different instruction set architectures (ISAs), and share a common memory to transfer data. Non-compiled statements are stored in the shared memory. The JIT compiler reads the non-compiled statements and compiles the statements into executable statements and stores them in the shared memory. The JIT compiler compiles the non-compiled statements destined for the first processor into executable instructions suitable for the first processor and statements destined for another type of processor (based on a different ISA) into instructions suitable for the other processor.

Abstract: The present invention provides for a method for computer program code optimization for a software managed cache in either a uni-processor or a multi-processor system. A single source file comprising a plurality of array references is received. The plurality of array references is analyzed to identify predictable accesses. The plurality of array references is analyzed to identify secondary predictable accesses. One or more of the plurality of array references is aggregated based on identified predictable accesses and identified secondary predictable accesses to generate aggregated references. The single source file is restructured based on the aggregated references to generate restructured code. Prefetch code is inserted in the restructured code based on the aggregated references. Software cache update code is inserted in the restructured code based on the aggregated references. Explicit cache lookup code is inserted for the remaining unpredictable accesses.