Patents by Inventor John Kevin Twynam
John Kevin Twynam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9269801Abstract: A normally-off-type HFET includes: an undoped AlwGa1-wN layer of t1 thickness, an undoped AlxGa1-xN layer of t2 thickness and an undoped GaN channel layer of tch thickness that are sequentially stacked; a source electrode and a drain electrode separated from each other and electrically connected to the channel layer; an undoped AlyGa1-yN layer of t3 thickness formed between the source electrode and the drain electrode on the channel layer; an AlzGa1-zN layer of t4 thickness formed in a shape of a mesa on a partial area of the AlyGa1-yN layer between the source electrode and the drain electrode; and a Schottky barrier type gate electrode formed on the AlzGa1-zN layer, in which conditions of y>x>w>z, t1>t4>t3 and 2wtch/(x?w)>t2>1 nm are satisfied.Type: GrantFiled: December 12, 2012Date of Patent: February 23, 2016Assignee: SHARP KABUSHIKI KAISHAInventor: John Kevin Twynam
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Publication number: 20140367742Abstract: A normally-off-type HFET includes: an undoped AlwGa1-wN layer of t1 thickness, an undoped AlxGa1-xN layer of t2 thickness and an undoped GaN channel layer of tch thickness that are sequentially stacked; a source electrode and a drain electrode separated from each other and electrically connected to the channel layer; an undoped AlyGa1-yN layer of t3 thickness formed between the source electrode and the drain electrode on the channel layer; an AlzGa1-zN layer of t4 thickness formed in a shape of a mesa on a partial area of the AlyGa1-yN layer between the source electrode and the drain electrode; and a Schottky barrier type gate electrode formed on the AlzGa1-zN layer, in which conditions of y>x>w>z, t1>t4>t3 and 2wtch/(x-w)>t2>1 nm are satisfied.Type: ApplicationFiled: December 12, 2012Publication date: December 18, 2014Applicant: Sharp Kabushiki KaishaInventor: John Kevin Twynam
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Patent number: 8723224Abstract: One embodiment of a semiconductor device according to the present invention includes a substrate, a base compound semiconductor layer layered on the substrate to form a base, a channel defining compound semiconductor layer layered on the base compound semiconductor layer to define a channel, and an impact ionization control layer that is layered within a layering range of the base compound semiconductor layer and controls the location of impact ionization, wherein the base compound semiconductor layer is formed of a first compound semiconductor, the channel defining compound semiconductor layer is formed of a second compound semiconductor, and the impact ionization control layer is formed of a third compound semiconductor that has a smaller band gap than the first compound semiconductor.Type: GrantFiled: September 14, 2012Date of Patent: May 13, 2014Assignee: Sharp Kabushiki KaishaInventors: Nobuyuki Ito, John Kevin Twynam
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Publication number: 20130306984Abstract: A normally-off-type HFET includes an undoped AlxGa1-xN layer of t1 thickness; a source electrode and a drain electrode separated from each other and electrically connected to the AlxGa1-xN layer; an undoped AlyGa1-yN layer of t2 thickness formed between the source electrode and the drain electrode on the AlxGa1-xN layer; an undoped AlzGa1-zN layer of t3 thickness formed on a partial area of the AlyGa1-yN layer between the source electrode and the drain electrode; and a Schottky barrier type gate electrode formed on the AlzGa1-zN layer, wherein conditions of y>x>z and t1>t3>t2 are satisfied.Type: ApplicationFiled: January 25, 2012Publication date: November 21, 2013Applicant: SHARP KABUSHIKI KAISHAInventor: John Kevin Twynam
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Publication number: 20130009166Abstract: One embodiment of a semiconductor device according to the present invention includes a substrate, a base compound semiconductor layer layered on the substrate to form a base, a channel defining compound semiconductor layer layered on the base compound semiconductor layer to define a channel, and an impact ionization control layer that is layered within a layering range of the base compound semiconductor layer and controls the location of impact ionization, wherein the base compound semiconductor layer is formed of a first compound semiconductor, the channel defining compound semiconductor layer is formed of a second compound semiconductor, and the impact ionization control layer is formed of a third compound semiconductor that has a smaller band gap than the first compound semiconductor.Type: ApplicationFiled: September 14, 2012Publication date: January 10, 2013Inventors: Nobuyuki ITO, John Kevin Twynam
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Patent number: 8288796Abstract: One embodiment of a semiconductor device according to the present invention includes a substrate, a base compound semiconductor layer layered on the substrate to form a base, a channel defining compound semiconductor layer layered on the base compound semiconductor layer to define a channel, and an impact ionization control layer that is layered within a layering range of the base compound semiconductor layer and controls the location of impact ionization, wherein the base compound semiconductor layer is formed of a first compound semiconductor, the channel defining compound semiconductor layer is formed of a second compound semiconductor, and the impact ionization control layer is formed of a third compound semiconductor that has a smaller band gap than the first compound semiconductor.Type: GrantFiled: May 21, 2010Date of Patent: October 16, 2012Assignee: Sharp Kabushiki KaishaInventors: Nobuyuki Ito, John Kevin Twynam
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Patent number: 8258544Abstract: A field-effect transistor provided with a substrate, a channel layer, a carrier supply layer, a source electrode, a drain electrode, a gate electrode, a first insulating layer that is laminated on the carrier supply layer between the source electrode and the drain electrode, and suppresses current collapse, an opening that is formed between an edge of the first insulating layer opposing the drain electrode and the drain electrode, and a second insulating layer that is laminated on the carrier supply layer exposed in the opening.Type: GrantFiled: March 19, 2010Date of Patent: September 4, 2012Assignee: Sharp Kabushiki KaishaInventors: Tetsuzo Nagahisa, John Kevin Twynam
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Patent number: 8004022Abstract: A field effect transistor includes a GaN epitaxial substrate, a gate electrode formed on an electron channel layer of the substrate, and source and drain electrodes arranged spaced apart by a prescribed distance on opposite sides of the gate electrode. The source and drain electrodes are in ohmic contact with the substrate. At an upper portion of the gate electrode, a field plate is formed protruding like a visor to the side of drain electrode. Between the electron channel layer of the epitaxial substrate and the field plate, a dielectric film is formed. The dielectric film is partially removed at a region immediately below the field plate, to be flush with a terminal end surface of the field plate. The dielectric film extends from a lower end of the removed portion to the drain electrode, to be overlapped on the drain electrode.Type: GrantFiled: January 6, 2009Date of Patent: August 23, 2011Assignee: Sharp Kabushiki KaishaInventors: Norimasa Yafune, John Kevin Twynam
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Publication number: 20110133205Abstract: A field-effect transistor provided with a channel layer, a carrier supply layer forming a heterojunction with the channel layer, a recessed portion recessed from a surface of the carrier supply layer, a first insulating layer formed at least along the recessed portion, a first gate electrode formed on the first insulating layer, a source electrode formed on one side of the recessed portion in a channel lengthwise direction, and a drain electrode formed on an opposite side of the recessed portion in the channel lengthwise direction. The recessed portion snakes in a direction intersecting the channel lengthwise direction, in the range of a channel length between the source electrode and the drain electrode.Type: ApplicationFiled: September 23, 2010Publication date: June 9, 2011Applicant: Sharp Kabushiki KaishaInventors: Tetsuzo Nagahisa, John Kevin Twynam
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Patent number: 7928480Abstract: A semiconductor device has a semiconductor layer, and a first electrode (Schottky electrode or MIS electrode) and a second electrode (ohmic electrode) which are formed on the semiconductor layer apart from each other. The first electrode has a cross section in the shape of a polygon. A second electrode-side corner of the polygon has an interior angle of which an outward extension line of a bisector crosses the semiconductor layer or the second electrode. The interior angle of such a second electrode-side corner is larger than 90°.Type: GrantFiled: November 30, 2006Date of Patent: April 19, 2011Assignee: Sharp Kabushiki KaishaInventors: Masaharu Yamashita, John Kevin Twynam
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Patent number: 7893461Abstract: In an electronic device of the present invention a gate Schottky electrode is formed on an active layer constructed of a GaN layer and an AlGaN layer, and a source ohmic electrode and a drain ohmic electrode are further formed on both sides of the gate Schottky electrode on the active layer. A dielectric layer (TiO2 layer) of a stepwise laminate structure is formed on the AlGaN layer so that the electric field distribution between the gate Schottky electrode and the drain ohmic electrode is substantially uniformed. The dielectric constant of TiO2 of the dielectric layer is made higher than the dielectric constant of GaN and AlGaN of the active layer.Type: GrantFiled: June 15, 2009Date of Patent: February 22, 2011Assignee: Sharp Kabushiki KaishaInventor: John Kevin Twynam
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Publication number: 20100314663Abstract: One embodiment of a semiconductor device according to the present invention includes a substrate, a base compound semiconductor layer layered on the substrate to form a base, a channel defining compound semiconductor layer layered on the base compound semiconductor layer to define a channel, and an impact ionization control layer that is layered within a layering range of the base compound semiconductor layer and controls the location of impact ionization, wherein the base compound semiconductor layer is formed of a first compound semiconductor, the channel defining compound semiconductor layer is formed of a second compound semiconductor, and the impact ionization control layer is formed of a third compound semiconductor that has a smaller band gap than the first compound semiconductor.Type: ApplicationFiled: May 21, 2010Publication date: December 16, 2010Inventors: Nobuyuki ITO, John Kevin Twynam
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Publication number: 20100308373Abstract: A field-effect transistor provided with a substrate, a channel layer, a carrier supply layer, a source electrode, a drain electrode, a gate electrode, a first insulating layer that is laminated on the carrier supply layer between the source electrode and the drain electrode, and suppresses current collapse, an opening that is formed between an edge of the first insulating layer opposing the drain electrode and the drain electrode, and a second insulating layer that is laminated on the carrier supply layer exposed in the opening.Type: ApplicationFiled: March 19, 2010Publication date: December 9, 2010Inventors: Tetsuzo Nagahisa, John Kevin Twynam
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Patent number: 7759760Abstract: A semiconductor switching element, wherein on a semiconductor layer formed on a substrate, or on a semiconductor substrate, a source electrode and a drain electrode are disposed at a predetermined interval in a direction along a surface of the substrate; and a second gate electrode is provided between the source electrode and the drain electrode, the second gate electrode is electrically connected with the source electrode and structured with two types of electrode material layers having Schottky barriers of different heights from each other.Type: GrantFiled: June 29, 2007Date of Patent: July 20, 2010Assignee: Sharp Kabushiki KaishaInventors: Norimasa Yafune, John Kevin Twynam
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Patent number: 7733105Abstract: In a voltage clamp circuit, a normally-on type field-effect transistor having a negative threshold voltage has a drain connected to an input node, a source connected to an output node and grounded via a resistance element, and a gate supplied with an output voltage of a variable direct-current power supply. When a voltage at the output node becomes higher than a clamping voltage because of voltage drop of the resistance element, the field-effect transistor is tuned off. Accordingly, the output voltage is limited to be at most the clamping voltage. Thus, a response speed is higher than those of conventional voltage clamp circuits using diodes or the like.Type: GrantFiled: June 13, 2008Date of Patent: June 8, 2010Assignee: Sharp Kabushiki KaishaInventors: Yoshiaki Nozaki, Hiroshi Kawamura, John Kevin Twynam, Masatomo Hasegawa
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Publication number: 20090250723Abstract: In an electronic device of the present invention a gate Schottky electrode is formed on an active layer constructed of a GaN layer and an AlGaN layer, and a source ohmic electrode and a drain ohmic electrode are further formed on both sides of the gate Schottky electrode on the active layer. A dielectric layer (TiO2 layer) of a stepwise laminate structure is formed on the AlGaN layer so that the electric field distribution between the gate Schottky electrode and the drain ohmic electrode is substantially uniformed. The dielectric constant of TiO2 of the dielectric layer is made higher than the dielectric constant of GaN and AlGaN of the active layer.Type: ApplicationFiled: June 15, 2009Publication date: October 8, 2009Inventor: John Kevin Twynam
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Publication number: 20090206373Abstract: A field effect transistor includes a GaN epitaxial substrate, a gate electrode formed on an electron channel layer of the substrate, and source and drain electrodes arranged spaced apart by a prescribed distance on opposite sides of the gate electrode. The source and drain electrodes are in ohmic contact with the substrate. At an upper portion of the gate electrode, a field plate is formed protruding like a visor to the side of drain electrode. Between the electron channel layer of the epitaxial substrate and the field plate, a dielectric film is formed. The dielectric film is partially removed at a region immediately below the field plate, to be flush with a terminal end surface of the field plate. The dielectric film extends from a lower end of the removed portion to the drain electrode, to be overlapped on the drain electrode.Type: ApplicationFiled: January 6, 2009Publication date: August 20, 2009Applicant: SHARP KABUSHIKI KAISHAInventors: Norimasa YAFUNE, John Kevin Twynam
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Patent number: 7566917Abstract: In an electronic device of the present invention a gate Schottky electrode is formed on an active layer constructed of a GaN layer and an AlGaN layer, and a source ohmic electrode and a drain ohmic electrode are further formed on both sides of the gate Schottky electrode on the active layer. A dielectric layer (TiO2 layer) of a stepwise laminate structure is formed on the AlGaN layer so that the electric field distribution between the gate Schottky electrode and the drain ohmic electrode is substantially uniformed. The dielectric constant of TiO2 of the dielectric layer is made higher than the dielectric constant of GaN and AlGaN of the active layer.Type: GrantFiled: September 27, 2005Date of Patent: July 28, 2009Assignee: Sharp Kabushiki KaishaInventor: John Kevin Twynam
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Publication number: 20080309355Abstract: In a voltage clamp circuit, a normally-on type field-effect transistor having a negative threshold voltage has a drain connected to an input node, a source connected to an output node and grounded via a resistance element, and a gate supplied with an output voltage of a variable direct-current power supply. When a voltage at the output node becomes higher than a clamping voltage because of voltage drop of the resistance element, the field-effect transistor is tuned off. Accordingly, the output voltage is limited to be at most the clamping voltage. Thus, a response speed is higher than those of conventional voltage clamp circuits using diodes or the like.Type: ApplicationFiled: June 13, 2008Publication date: December 18, 2008Inventors: Yoshiaki Nozaki, Hiroshi Kawamura, John Kevin Twynam, Masatomo Hasegawa
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Publication number: 20080006898Abstract: A semiconductor switching element, wherein on a semiconductor layer formed on a substrate, or on a semiconductor substrate, a source electrode and a drain electrode are disposed at a predetermined interval in a direction along a surface of the substrate; and a second gate electrode is provided between the source electrode and the drain electrode, the second gate electrode is electrically connected with the source electrode and structured with two types of electrode material layers having Schottky barriers of different heights from each other.Type: ApplicationFiled: June 29, 2007Publication date: January 10, 2008Applicant: Sharp Kabushiki KaishaInventors: Norimasa Yafune, John Kevin Twynam