Abstract: According to some embodiments, a battery cluster controller includes a serial interface configured to receive waveform data and a rank over a serial communication bus, a processor configured to generate a switching parameter based on the rank and the waveform data, and a modulation unit configured with the switching parameter to generate a bridge configuration signal to control a bridge for selectively connecting a battery element to an output terminal to generate a first component of a waveform.

Abstract: According to some embodiments, a battery cluster controller includes a serial interface configured to receive waveform data and a rank over a serial communication bus, a processor configured to generate a switching parameter based on the rank and the waveform data, and a modulation unit configured with the switching parameter to generate a bridge configuration signal to control a bridge for selectively connecting a battery element to an output terminal to generate a first component of a waveform.

Abstract: According to some embodiments, a method includes connecting a first cluster controller of a first battery cluster to a serial communication bus, connecting a second cluster controller of a second battery cluster to the serial communication bus, sending synchronization data to the first cluster controller and the second cluster controller over the serial communication bus, controlling a first bridge of the first battery cluster to connect a first battery terminal of the first battery cluster to an output terminal based on the synchronization data and a first rank assigned to the first battery cluster to generate a first component of a waveform, and controlling a second bridge of the second cluster to connect a second battery terminal of the second battery cluster to the output terminal based on the synchronization data and a second rank assigned to the second battery cluster to generate a second component of the waveform.

Abstract: Apparatuses and methods of mutual-capacitance sensing with a capacitance-sensing circuit, such as a self-capacitance sensing device (CSD). One apparatus includes an input node coupled to a capacitance sense pin to couple to a first electrode of a sense array, a transmit (TX) signal generation circuit to generate a TX signal to drive a second electrode of the sense array, logic circuitry coupled to the TX signal generation circuit and the input node. The logic circuitry is configured to selectively couple a first capacitor to the input node and a second capacitor to the input node timed with the TX signal. The apparatus further includes an analog-to-digital converter (ADC) coupled to receive a receive (RX) signal from the input node and to convert the RX signal into a digital value, the digital value representing a mutual capacitance between the first electrode and the second electrode.

Abstract: A voltage-controlled oscillator is provided that avoids use of any crystal resonator, or any resonator that is external to and not integrated upon the voltage-controlled oscillator monolithic substrate. The present oscillator can receive two or more parameters that would likely have an affect on the oscillator frequency, yet the oscillator includes compensating transfer functions that will remove, or correct for, that effect. Transfer functions involve electronic subsystems implemented in hardware or software that receive the input parameter that has changed from a nominal value, and will note the drift in output frequency, yet will compensate for that drift so that the output frequency remains near the nominal value. The voltage-controlled oscillator preferably is an LCVCO, and the transfer function outputs can be summed to take into account multiple parameter changes.

Abstract: In one embodiment, an antifuse cell includes a select transistor, a blocking transistor, and an antifuse. The select transistor allows for selection of the antifuse cell among an array of antifuse cells, while the blocking transistor limits the amount of voltage that may be directly applied to the select transistor. The antifuse may comprise a capacitor. In another embodiment, current used to program an antifuse cell is controlled using a programming current regulator. The programming current regulator may include components that form a current mirror with components of the antifuse cell to tightly control programming current through the antifuse. In yet another embodiment, dynamic current flowing through a substrate of an antifuse cell is limited using a current limiting resistor directly in series with an antifuse of the antifuse cell. The current limiting resistor minimizes or prevents excessive programming current.

Abstract: In one embodiment, an antifuse cell includes a select transistor, a blocking transistor, and an antifuse. The select transistor allows for selection of the antifuse cell among an array of antifuse cells, while the blocking transistor limits the amount of voltage that may be directly applied to the select transistor. The antifuse may comprise a capacitor. In another embodiment, current used to program an antifuse cell is controlled using a programming current regulator. The programming current regulator may include components that form a current mirror with components of the antifuse cell to tightly control programming current through the antifuse. In yet another embodiment, dynamic current flowing through a substrate of an antifuse cell is limited using a current limiting resistor directly in series with an antifuse of the antifuse cell. The current limiting resistor minimizes or prevents excessive programming current.

Abstract: An apparatus comprising a latch circuit, a non-volatile storage circuit, and a switching circuit. The latch circuit may be configured to be dynamically programmable. The non-volatile storage circuit may be configured to be re-programmable. The switching circuit may be configured to transfer data from (i) the non-volatile memory element into the latch circuit in response to a first control signal and (ii) the latch circuit into the non-volatile memory circuit in response to a second control signal.

Abstract: An apparatus comprising a latch circuit, a non-volatile storage circuit, and a switching circuit. The latch circuit may be configured to be dynamically programmable. The non-volatile storage circuit may be configured to be re-programmable. The switching circuit may be configured to transfer data from (i) the non-volatile memory element into the latch circuit in response to a first control signal and (ii) the latch circuit into the non-volatile memory circuit in response to a second control signal.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to receive a device input signal. The apparatus may be configured to perform a predefined function in response to the device input signal during normal operation. The second circuit may be configured to determine when the device input signal is invalid according to a predetermined parameter. The second circuit may be configured to generate a function control signal in response to the predetermined parameter. The function control signal may be configured to direct the apparatus to perform a second predetermined function. The second predetermined function may be different than the first predetermined function.