Abstract: A wafer edge defect inspection method and apparatus for use in an integrated circuit fabrication system includes an image capturing device for capturing images of the edges of wafers, a database in which the images are stored and accessible for analysis and a computer for analyzing the images of one or more wafer edges to locate edge defects and for evaluating the performance of the fabrication system. The inspection and data storage are performed automatically. The database storage enables detailed analysis of many wafers and fabrication process steps.

Abstract: A method of qualifying a process tool includes steps of: (a) finding a plurality of pre-scan defect locations on a surface of a semiconductor wafer; (b) subjecting the semiconductor wafer to processing by the process tool; (c) finding a plurality of post-scan defect locations on the surface of the semiconductor wafer; and (d) calculating a plurality of defect locations added by the process tool from the pre-scan defect locations and the post-scan defect locations.

Abstract: A method of qualifying a process tool includes steps of: (a) finding a plurality of pre-scan defect locations on a surface of a semiconductor wafer; (b) subjecting the semiconductor wafer to processing by the process tool; (c) finding a plurality of post-scan defect locations on the surface of the semiconductor wafer; and (d) calculating a plurality of defect locations added by the process tool from the pre-scan defect locations and the post-scan defect locations.

Abstract: A wafer edge defect inspection method and apparatus for use in an integrated circuit fabrication system includes an image capturing device for capturing images of the edges of wafers, a database in which the images are stored and accessible for analysis and a computer for analyzing the images of one or more wafer edges to locate edge defects and for evaluating the performance of the fabrication system. The inspection and data storage are performed automatically. The database storage enables detailed analysis of many wafers and fabrication process steps.

Abstract: A computerized system for analyzing information associated with a process unit. A database contains historical information relating to previously compiled information. A secure input receives criteria from a restricted source. A computer mathematically determines a limit based upon the criteria. An open input receives the information associated with the process unit from multiple test locations. A compiler selectively adds to the database of historical information the information. The computer also selects at least a portion of the information based upon selection criteria. In addition, the computer manipulates the selected information based upon manipulation criteria. The manipulated information is compared against the limit. An output indicates a first disposition of the process unit when the manipulated information violates the limit. The output indicates a second disposition of the process unit when the manipulated information does not violate the limit.