Abstract: A novel explosion-proof motor, which includes an integrated explosion-proof housing. In some embodiments, the integrated explosion-proof housing contains various electronic components that support the operation of the explosion-proof motor. To this end, embodiments of the explosion-proof motor may include a stator having an end ring, a plurality of stator coils extending from a core, and an end bracket fitted to the stator end ring to form a generally circumferential flame path. The end bracket may include an inner volume on one side thereof for receiving the stator coils, and an integrated explosion-proof housing on the other side. To reduce the number of explosion-proof seals, the inner volume and integrated explosion-proof housing may share the circumferential flame path to enclose their respective volumes.

Abstract: A system is provided that includes a CPU, a graphical user interface coupled to the CPU, and a memory coupled to the CPU. The memory stores a bump map application and a data extraction application executed by the CPU. The bump map application displays a plurality of editable textual character groups representative of a plurality of bumps. The textual character groups are arranged on the graphical user interface according to a relative coordinate position of the bumps with respect to an origin. The data extraction application automatically extracts data from the bump map application for use by a router application.

Abstract: A drive device for mining machines, especially for chain-hauled longwall operating equipment, comprising a drive motor (1) disposed in a motor housing (2) and with a flange (3) for connecting the drive motor (1) to a gear unit (30), at least one measurement-collecting device for detecting operating states of the drive motor (1) and/or of the gear unit (30) and a drive computer for actuating the drive motor (1) and/or for actuating components of the gear unit (30), in which at least one receiving casing (8) for the measurement-collecting device and/or the drive computer is disposed on the outside of the motor housing (2).

Abstract: In at least some embodiments, a system may comprise a CPU, a graphical user interface coupled to the CPU, and a memory coupled to the CPU. The memory stores a bump map application and a data extraction application executed by the CPU, wherein the bump map application displays a plurality of editable textual character groups representative of a plurality of bumps that are arranged on the graphical user interface according to a relative coordinate position of the bumps with respect to an origin. In some embodiments, the data extraction application automatically extracts data from the bump map application for use by a router application.

Abstract: A beacon for providing a reference location on an integrated circuit is disclosed. The beacon comprises a device capable of emitting radiation and disposed at a corresponding reference location on the integrated circuit, wherein the device is capable of being controlled independent of integrated circuit operations.

Abstract: A semiconductor structure having: semiconductor devices formed in an inner region of a semiconductor chip; a seal ring formed in the chip and disposed about the inner region; and, a plurality of trenches formed along a surface of the chip. The trenches are disposed in a corner region of the chip. A portion of the seal ring is disposed between the trenches and the inner region of the chip. The trenches are disposed along axes oblique to outer edges of the chip. A method is provided for encapsulating a semiconductor chip. The method includes the steps of: providing a semiconductor chip having active semiconductor devices in an inner region of the semiconductor chip and a seal ring in the chip about the inner region; and, forming a plurality of trenches in the chip, a portion of the seal ring being formed between the trenches and the inner region of the chip. A cover is formed having bottom portions in the trenches and on the passivation layer.

Abstract: A driver circuit for limiting electrical noise on a quiescent signal is provided which includes a Transition High Driver circuit, a Transition Low Driver circuit, a Quiescent High Driver circuit, and a Quiescent Low Driver circuit. The driver circuit comprises means for driving an electrical signal with a presumed noisy Transition Power Supply network while it is transitioning from a low voltage level to a high voltage level or vice versa. The signal is driven by the Transition Power Supply network until the electrical signal reaches its quiescent voltage level. At this time, the signal is no longer driven by the Transition Power Supply network but rather by a presumed clean Quiescent Power Supply network. In this manner, noise from transitioning signals is prevented from coupling onto quiescent signals.

Abstract: A multiplier in a floating point processor includes a circuit to determine for each bit of the multiplier operand a 3 times booth recode and a booth recode multiplier array which implements a 3 times booth recode multiplication. The multiplier includes logic to determine a fast sign extend to replace bit positions shifted in the array as well as a rounding adder to provide a rounded result while determining the final result from the booth recode multiplier. The multiplier also includes a circuit to determine a contribution to the final multiplication result from a lower order product with out forming the entire product.

Abstract: A pipelined floating point processor including an add pipe for performing floating point additions is described. The add pipe includes a circuit to predict a normalization shift amount from examination of input operands, a circuit to determine the "Sticky bit" from the input operands, and a rounding adder which adds a pair of operands and rounds the result in a single pipeline stage operation. The rounding adder incorporates effects due to rounding in select logic for a series of carry select adders. The adder also aligns the datapath to permit economical storage and retrieval of floating point and integer operands for floating point or conversions operations. The floating point processor also includes in the adder pipeline a divider circuit include a quotient register having overflow quotient bit positions to detect the end of a division operation.

Abstract: A pipelined floating point processor including an add pipe for performing floating point additions described. The add pipe includes a circuit to predict a normalization shift amount from examination of input operands, a circuit to determine the "Sticky bit" from the input operands, and a rounding adder which adds a pair of operands and rounds the result in a single pipeline stage operation. The rounding adder incorporates effects due to rounding in select logic for a series of carry select adders. The adder also aligns the datapath to permit economical storage and retrieval of floating point and interger operands for floating point or conversions operations. The floating point processor also includes in the adder pipeline a divider circuit include a quotient register having overflow quotient bit positions to detect the end of a division operation.

Abstract: Apparatus and method for expediting the alignment of the fraction portion of operands in floating point operations. The alignment is performed in the arthmetic logic unit where the argument of the operand A exponent is subtracted from the argument of the operand B exponent. Because the result B-A can be a negative quantity, the result A-B can also be required. The arthmetic logic unit of the present invention provides additional apparatus for simultaneously determining B-A and A-B. The additional apparatus includes components in the propagate bit and generate bit cell for determining an auxiliary generate bit; an additional carry-chain array for combining the carry-in signal, the propagate bit and the auxiliary generate bit; and selection circuits for selecting the appropriate result.