Abstract: A mechanism is provided for packaging a multiple socket, one-hop symmetric multiprocessor topology. The mechanism connects each of a first plurality of processor modules to a first multiple-socket planar via a respective one of a first plurality of land grid array (LGA) connectors. The mechanism connects the first multiple-socket planar to a first side of a redistribution card via a second plurality of LGA connectors. The mechanism connects each of a second plurality of processor modules to a second multiple-socket planar via a respective one of a third plurality of LGA connectors. The mechanism connects the second multiple-socket planar to a second side of the redistribution card via a fourth plurality of LGA connectors.

Abstract: A mechanism is provided for packaging a multiple socket, one-hop symmetric multiprocessor topology. The mechanism connects each of a first plurality of processor modules to a first multiple-socket planar via a respective one of a first plurality of land grid array (LGA) connectors. The mechanism connects the first multiple-socket planar to a first side of a redistribution card via a second plurality of LGA connectors. The mechanism connects each of a second plurality of processor modules to a second multiple-socket planar via a respective one of a third plurality of LGA connectors. The mechanism connects the second multiple-socket planar to a second side of the redistribution card via a fourth plurality of LGA connectors.

Abstract: A method and apparatus are provided for implementing enhanced heat sink loading for cooling an electronic module having one or more semiconductor chips. The apparatus includes an electronic module having one or more semiconductor chips; a heat sink; a heat sink load bearing member further comprising raised points; a load spring passing through the heat sink, the load spring having a latch arm at a first end and a load screw at a second end actuating the load spring, the load spring when actuated is configured to bear against the raised points to equalize pressure distribution over one or more semiconductor chips on the electronic module.

Abstract: A mechanism is provided for packaging a multiple socket, one-hop symmetric multiprocessor topology. The mechanism connects each of a first plurality of processor modules to a first multiple-socket planar via a respective one of a first plurality of land grid array (LGA) connectors. The mechanism connects the first multiple-socket planar to a first side of a redistribution card via a second plurality of LGA connectors. The mechanism connects each of a second plurality of processor modules to a second multiple-socket planar via a respective one of a third plurality of LGA connectors. The mechanism connects the second multiple-socket planar to a second side of the redistribution card via a fourth plurality of LGA connectors.

Abstract: A mechanism is provided for packaging a multiple socket, one-hop symmetric multiprocessor topology. The mechanism connects each of a first plurality of processor modules to a first multiple-socket planar via a respective one of a first plurality of land grid array (LGA) connectors. The mechanism connects the first multiple-socket planar to a first side of a redistribution card via a second plurality of LGA connectors. The mechanism connects each of a second plurality of processor modules to a second multiple-socket planar via a respective one of a third plurality of LGA connectors. The mechanism connects the second multiple-socket planar to a second side of the redistribution card via a fourth plurality of LGA connectors.

Abstract: Mechanisms for interconnecting and distributing signals and power between PCBs are provided. A first PCB having land grid arrays (LGAs) and a first wiring layer designed for interconnect components on the first PCB, and a second wiring layer for connecting the components to a second PCB, are provided. The second PCB has opposed parallel first and second surfaces, the first surface having a LGA. A wiring layer designed to interconnect components on the second PCB, and a layer for interconnecting the components on the second PCB with the components on the first PCB, are provided. A first interposer couples to a LGA of a first surface of the first PCB and connects a component to the first PCB. A second interposer is sandwiched between and couples to a LGA of a second surface of the first PCB and to the LGA of the first surface of the second PCB.

Abstract: A method and apparatus are provided for implementing enhanced heat sink loading for cooling an electronic module having one or more semiconductor chips. The apparatus includes an electronic module having one or more semiconductor chips; a heat sink; a heat sink load bearing member further comprising raised points; a load spring passing through the heat sink, the load spring having a latch arm at a first end and a load screw at a second end actuating the load spring, the load spring when actuated is configured to bear against the raised points to equalize pressure distribution over one or more semiconductor chips on the electronic module.

Abstract: A method and apparatus are provided for implementing electrical connection of two large circuit cards through multiple discrete land grid array (LGA) sites. Each of the circuit cards includes a plurality of LGA sites. A first circuit card includes a plurality of LGA interposers locally aligned at the respective LGA sites of the first circuit card. A board-to-board connection hardware assembly connecting a second circuit card to the first circuit card includes a elongated carrier defining a cavity receiving a plurality of load springs coupled to an associated bearing block for loading and maintaining flatness of the LGA sites.

Abstract: A method and apparatus are provided for implementing electrical connection of two large circuit cards through multiple discrete land grid array (LGA) sites. Each of the circuit cards includes a plurality of LGA sites. A first circuit card includes a plurality of LGA interposers locally aligned at the respective LGA sites of the first circuit card. A board-to-board connection hardware assembly connecting a second circuit card to the first circuit card includes a elongated carrier defining a cavity receiving a plurality of load springs coupled to an associated bearing block for loading and maintaining flatness of the LGA sites.

Abstract: A system, method, and motherboard assembly are described for interconnecting and distributing signals and power between co-planar boards that function as a single motherboard. The motherboard assembly includes a multilayered first printed circuit board having opposed parallel first and second surfaces, each having at least one land grid array (LGA) disposed thereon. The assembly further includes at least one wiring layer (Y) designed to only electrically interconnect components on or within the first PCB, and at least one wiring layer (X) designed to only electrically connect the components on the first PCB to a multilayered second PCB. The multilayered second PCB has opposed parallel first and second surfaces, the first surface having at least one LGA disposed thereon.

Abstract: Mechanisms for interconnecting and distributing signals and power between PCBs are provided. A first PCB having land grid arrays (LGAs) and a first wiring layer designed for interconnect components on the first PCB, and a second wiring layer for connecting the components to a second PCB, are provided. The second PCB has opposed parallel first and second surfaces, the first surface having a LGA. A wiring layer designed to interconnect components on the second PCB, and a layer for interconnecting the components on the second PCB with the components on the first PCB, are provided. A first interposer couples to a LGA of a first surface of the first PCB and connects a component to the first PCB. A second interposer is sandwiched between and couples to a LGA of a second surface of the first PCB and to the LGA of the first surface of the second PCB.

Abstract: A method and apparatus are provided for implementing loading and heat removal for a hub module assembly. The hub module assembly includes a hub chip and a plurality of optical modules attached by land grid array (LGA) assembly disposed on a top surface metallurgy (TSM) LGA residing on a hub ceramic substrate. The ceramic substrate is connected to a circuit board through a bottom surface metallurgy (BSM) LGA assembly. A base alignment ring includes a plurality of alignment features for engaging the circuit board and locating an LGA interposer of the BSM LGA assembly. Each of a pair of top alignment rings includes cooperating alignment features for engaging and locating a respective LGA interposer of respective LGA sites of the TSM LGA assembly. The two LGA interposers of the TSM LGA assembly align, retain, and make the electrical connection between the optical modules and the hub chip.

Abstract: An apparatus is disclosed for aligning socket housing segments for an area array device. Each socket housing segment includes at least a first surface and a second surface, with the second surface opposite the first surface. The second surface of each socket housing segment provides electrical connections for a portion of the area array device. Socket contact pads are disposed on the first surfaces of the plurality of socket housing segments. The socket contact pads correspond to substrate contact pads disposed on a substrate. One or more alignment structures are disposed at a space between the socket housing segments. Each alignment structure is coupled to at least two of the socket housing segments. The one or more alignment structures maintain a predetermined alignment of each socket housing segment so that the socket contact pads align with the substrate contact pads during a surface mount connection process.

Abstract: A method and apparatus are provided for implementing loading and heat removal for a hub module assembly. The hub module assembly includes a hub chip and a plurality of optical modules attached by land grid array (LGA) assembly disposed on a top surface metallurgy (TSM) LGA residing on a hub ceramic substrate. The ceramic substrate is connected to a circuit board through a bottom surface metallurgy (BSM) LGA assembly. A base alignment ring includes a plurality of alignment features for engaging the circuit board and locating an LGA interposer of the BSM LGA assembly. Each of a pair of top alignment rings includes cooperating alignment features for engaging and locating a respective LGA interposer of respective LGA sites of the TSM LGA assembly. The two LGA interposers of the TSM LGA assembly align, retain, and make the electrical connection between the optical modules and the hub chip.

Abstract: A method, a computer program product, and an apparatus is provided for scheduling meetings which includes (1) evaluating a set of proposed meetings, (2) creating a number of calendars, each calendar containing schedule date for the proposed meetings, (3) ranking each calendar according to a calendar evaluation criteria and providing the ranking data with the calendar, and (4) displaying several of the calendars and their respective ranking data.

Abstract: An apparatus is disclosed for aligning socket housing segments for an area array device. Each socket housing segment includes at least a first surface and a second surface, with the second surface opposite the first surface. The second surface of each socket housing segment provides electrical connections for a portion of the area array device. Socket contact pads are disposed on the first surfaces of the plurality of socket housing segments. The socket contact pads correspond to substrate contact pads disposed on a substrate. One or more alignment structures are disposed at a space between the socket housing segments. Each alignment structure is coupled to at least two of the socket housing segments. The one or more alignment structures maintain a predetermined alignment of each socket housing segment so that the socket contact pads align with the substrate contact pads during a surface mount connection process.

Abstract: A method and enhanced connector guide block structures implement robust connector assembly including robust Surface Mount Technology (SMT) connector assembly. A connector guide block includes a printed wiring board (PWB) mating face including at least one mounting screw hole provided within a mounting portion for receiving a mounting screw. The connector guide block is assembled with a printed wiring board (PWB) by inserting a respective non-bonding screw through an aligned opening in the PWB into guide block mounting hole and a gap is defined from an upper surface of the PWB below the guide block mounting portion. The gap is filled with an electrically nonconductive underfill material and cured. Another connector guide block structure includes an upper connector guide block portion and a lower connector guide block portion with a gap between the guide block portions filled with a selected electrically nonconductive underfill material and cured.

Abstract: A system, method, and motherboard assembly are described for interconnecting and distributing signals and power between co-planar boards that function as a single motherboard. The motherboard assembly includes a multilayered first printed circuit board having opposed parallel first and second surfaces, each having at least one land grid array (LGA) disposed thereon. The assembly further includes at least one wiring layer (Y) designed to only electrically interconnect components on or within the first PCB, and at least one wiring layer (X) designed to only electrically connect the components on the first PCB to a multilayered second PCB. The multilayered second PCB has opposed parallel first and second surfaces, the first surface having at least one LGA disposed thereon.

Abstract: A cold plate assembly includes a cold plate with at least two plumbing ports. The cold plate assembly further includes a spring plate assembly, which applies an actuation load to the cold plate. The spring plate assembly includes a spring plate and a spring pin moveable in a slot of the spring plate assembly to maintain the actuation load. The actuation load is configured to mechanically actuate the cold plate to a module.

Abstract: A method and enhanced connector guide block structures implement robust connector assembly including robust Surface Mount Technology (SMT) connector assembly. A connector guide block includes a printed wiring board (PWB) mating face including at least one mounting screw hole provided within a mounting portion for receiving a mounting screw. The connector guide block is assembled with a printed wiring board (PWB) by inserting a respective non-bonding screw through an aligned opening in the PWB into guide block mounting hole and a gap is defined from an upper surface of the PWB below the guide block mounting portion. The gap is filled with an electrically nonconductive underfill material and cured. Another connector guide block structure includes an upper connector guide block portion and a lower connector guide block portion with a gap between the guide block portions filled with a selected electrically nonconductive underfill material and cured.