Patents by Inventor John L. Forneris

John L. Forneris has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4567645
    Abstract: The method is comprised of the following steps:implanting arsenic ions through a thin screen oxide layer in the regions of a P type silicon substrate where subcollectors are to be formed, at a dose less than 2.10.sup.16 at/cm.sup.2, partially etching said screen oxide layer to remove the upper portion, containing contaminating ions exposing to an oxygen ambiant to approximately reconstitute original thickness of the screen oxide layer and then annealing in an inert atmosphere, the substrate, to heal damages and distribute arsenic atoms in the substrate. It has been discovered that the step of reconstituting the original thickness of the screen oxide layer in an oxygen ambient, has the unexpected effect of permitting the subsequent growth of an absolutely defect free epitaxial layer.
    Type: Grant
    Filed: September 16, 1983
    Date of Patent: February 4, 1986
    Assignee: International Business Machines Corporation
    Inventors: Richard A. Cavanagh, John L. Forneris, Gregory B. Forney, George Hrebin, Jr., Ronald A. Knapp
  • Patent number: 4135097
    Abstract: In an ion beam apparatus a structure for controlling the surface potential of the target comprising an electron source adjacent to the beam for providing electrons to the beam and means between the target and source for inhibiting rectilinear radiations, i.e., electron and other particle and photon radiations between said source and said target. This prevents heating of the target by the electron source and cross-contamination between the source and the target.
    Type: Grant
    Filed: May 5, 1977
    Date of Patent: January 16, 1979
    Assignee: International Business Machines Corporation
    Inventors: John L. Forneris, William W. Hicks, John H. Keller, Charles M. McKenna, James A. Seirmarco
  • Patent number: 4060427
    Abstract: A region in an integrated circuit substrate is formed by first ion implanting impurities of a selected conductivity-determining type into a semiconductor substrate through at least one aperture in a masking electrically insulative layer, and then diffusing a conductivity-determining impurity of the same type through the same aperture into said substrate.The method has particular application when the electrically insulative layer is a composite of two layers, e.g., a top layer of silicon nitride and a bottom layer of silicon dioxide and the aperture is thus a pair of registered openings respectively through said silicon nitride and silicon dioxide layers, and the aperture through the silicon dioxide layer has greater lateral dimensions than that in the silicon nitride layer to provide an undercut beneath the silicon nitride ion implantation barrier layer.
    Type: Grant
    Filed: April 5, 1976
    Date of Patent: November 29, 1977
    Assignee: IBM Corporation
    Inventors: Conrad A. Barile, Robert M. Brill, John L. Forneris, Joseph Regh