Patents by Inventor John L. Mauer, IV

John L. Mauer, IV has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5264328
    Abstract: The present invention provides a method for determining the development endpoint in a X-ray lithographic process. Endpoint is determined by visually observing resist test field patterns through a microscope during the developing step. During the developing, changing test field patterns are formed because test field locations each had been exposed simultaneously to different radiation doses. These different doses are produced when radiation passes through a mask containing a plurality of different size radiation attenuators. When the changing test field pattern matches a known pattern, which is correlated to the desired development endpoint, the workpiece is removed from the developing step.
    Type: Grant
    Filed: April 24, 1992
    Date of Patent: November 23, 1993
    Assignee: International Business Machines Corporation
    Inventors: Ronald A. DellaGuardia, John L. Mauer, IV, David E. Seeger
  • Patent number: 4796069
    Abstract: A method is disclosed for fabricating a small area, self aligned guard ring in a Schottky barrier diode. A vertically-walled hole is anisotropically etched completely through a dielectric layer on a silicon substrate. A layer of doped polycrystalline silicon is deposited over the apertured dielectric layer. The polycrystalline silicon is reactively ion etched away to leave only a lining about the perimeter of the hole in the dielectric layer. The structure is heated to diffuse the dopant from the lining into the substrate. Schottky diode metal is deposited on the substrate exposed through the lined aperture in the dielectric layer.
    Type: Grant
    Filed: June 18, 1987
    Date of Patent: January 3, 1989
    Assignee: International Business Machines Corporation
    Inventors: Narasipur G. Anantha, Harsaran S. Bhatia, Santosh P. Gaur, John L. Mauer, IV
  • Patent number: 4691435
    Abstract: A method is disclosed for fabricating a small area, self aligned guard ring in a Schottky barrier diode. A vertically-walled hole is anisotropically etched completely through a dielectric layer on a silicon substrate. A layer of doped polycrystalline silicon is deposited over the apertured dielectric layer. The polycrystalline silicon is reactively ion etched away to leave only a lining about the perimeter of the hole in the dielectric layer. The structure is heated to diffuse the dopant from the lining into the substrate. Schottky diode metal is deposited on the substrate exposed through the lined aperture in the dielectric layer.
    Type: Grant
    Filed: May 13, 1981
    Date of Patent: September 8, 1987
    Assignee: International Business Machines Corporation
    Inventors: Narasipur G. Anantha, Harsaran S. Bhatia, Santosh P. Gaur, John L. Mauer, IV
  • Patent number: 4688069
    Abstract: An integrated circuit structure having substrate contacts formed as a part of the isolation structure and the method to form such structure is described. The integrated circuit structure is composed of a monocrystalline silicon body having a pattern of dielectric isolation surrounding regions of the monocrystalline silicon in the body. The dielectric isolation pattern includes a recessed dielectric portion at and just below the surface of the integrated circuit and a deep portion which extends through the recessed dielectric portion and extends further into the monocrystalline silicon body than the recessed portion. A highly doped polycrystalline silicon substrate contact is located within the deep portion of the pattern of isolation. The substrate contact extends from the surface of the pattern of isolation down to the bottom of the deep portion of the isolation where the contact electrically connects to the silicon body.
    Type: Grant
    Filed: December 6, 1985
    Date of Patent: August 18, 1987
    Assignee: International Business Machines Corporation
    Inventors: Richard C. Joy, Bernard M. Kemlage, John L. Mauer, IV
  • Patent number: 4494004
    Abstract: An electron beam method and apparatus, for writing patterns, such as on semiconductor wafers, in which the writing field is divided into a large number of overlapping subfields with a predetermined periodicity. Subfield to subfield moves are made in a stepped sequential scan, such as raster, while patterns, within a subfield, are addressed using vector scan and written using a sequential scan. Significant improvement in throughput results by the use of this electron beam method and apparatus which preferably employs magnetic deflection for the sequential scanning the subfields and electric deflection for vector scanning within the subfield.
    Type: Grant
    Filed: July 1, 1983
    Date of Patent: January 15, 1985
    Assignee: International Business Machines Corporation
    Inventors: John L. Mauer, IV, Michel S. Michail, Ollie C. Woodard
  • Patent number: 4454647
    Abstract: An integrated circuit structure having substrate contacts formed as a part of the isolation structure and the method to form such structure is described. The integrated circuit structure is composed of a monocrystalline silicon body having a pattern of dielectric isolation surrounding regions of the monocrystalline silicon in the body. The dielectric isolation pattern includes a recessed dielectric portion at and just below the surface of the integrated circuit and a deep portion which extends through the recessed dielectric portion and extends further into the monocrystalline silicon body than the recessed portion. A highly doped polycrystalline silicon substrate contact is located within the deep portion of the pattern of isolation. The substrate contact extends from the surface of the pattern of isolation down to the bottom of the deep portion of the isolation where the contact electrically connects to the silicon body.
    Type: Grant
    Filed: August 27, 1981
    Date of Patent: June 19, 1984
    Assignee: International Business Machines Corporation
    Inventors: Richard C. Joy, Bernard M. Kemlage, John L. Mauer, IV
  • Patent number: 4454646
    Abstract: An integrated circuit structure having substrate contacts formed as a part of the isolation structure and method for making the same is described. The integrated circuit structure is composed of a monocrystalline silicon body having a pattern of dielectric isolation surrounding regions of the monocrystalline silicon in the body. The dielectric isolation pattern includes a recessed dielectric portion at and just below the surface of the integrated circuit and a deep portion which extends from the side of the recessed dielectric portion opposite to that portion at the surface of said body into the monocrystalline silicon body. A highly doped polycrystalline silicon substrate contact is located within the deep portion of the pattern of isolation.
    Type: Grant
    Filed: August 27, 1981
    Date of Patent: June 19, 1984
    Assignee: International Business Machines Corporation
    Inventors: Richard C. Joy, Bernard M. Kemlage, John L. Mauer, IV
  • Patent number: 4447824
    Abstract: Use of a dual composite mask for a lift-off multi-layered structure process in which a base component layer acts as an etch stop for reactive ion etching of overlying layers.
    Type: Grant
    Filed: September 10, 1982
    Date of Patent: May 8, 1984
    Assignee: International Business Machines Corporation
    Inventors: Joseph S. Logan, John L. Mauer, IV, Laura B. Rothman, Geraldine C. Schwartz, Charles L. Standley
  • Patent number: 4389294
    Abstract: A method for eliminating deposited residues, for example polysilicon residue, on vertical silicon dioxide sidewalls that have been reactive ion etched includes reshaping the sidewalls to have a slope of at least +30.degree. relative to the vertical direction of the sidewall.
    Type: Grant
    Filed: June 30, 1981
    Date of Patent: June 21, 1983
    Assignee: International Business Machines Corporation
    Inventors: Narasipur G. Anantha, Harsaran S. Bhatia, John L. Mauer, IV, Homi G. Sarkary
  • Patent number: 4367119
    Abstract: Use of a dual composite mask for a lift-off multi-layered structure process in which a base component layer acts as an etch stop for reactive ion etching of overlying layers.
    Type: Grant
    Filed: August 18, 1980
    Date of Patent: January 4, 1983
    Assignee: International Business Machines Corporation
    Inventors: Joseph S. Logan, John L. Mauer, IV, Laura B. Rothman, Geraldine C. Schwartz, Charles L. Standley
  • Patent number: 4222792
    Abstract: A planar deep oxide isolation process for providing deep wide silicon dioxide filled trenches in the planar surface of a silicon semiconductor substrate, said process comprising the steps:(a) forming deep wide trenches in the planar surface of the silicon substrate;(b) forming a thin layer of silicon dioxide on the planar surface of the silicon substrate and the exposed silicon surfaces of said deep wide trenches;(c) applying resin glass (polysiloxane) to the planar surface of said semiconductor substrate and within said deep wide trenches;(d) spinning off at least a portion of the resin glass on the planar surface of the substrate;(e) baking the substrate at a low temperature;(f) exposing the resin glass contained within the deep wide trenches of substrate to the energy of an E-beam;(g) developing the resin glass contained on said substrate in a solvent;(h) heating said substrate in oxygen to convert said resin glass contained within said deep wide trenches to silicon dioxide;(i) depositing a layer of silico
    Type: Grant
    Filed: September 10, 1979
    Date of Patent: September 16, 1980
    Assignee: International Business Machines Corporation
    Inventors: Reginald F. Lever, John L. Mauer, IV, Alwin E. Michel, Laura B. Rothman