Patents by Inventor John L. Ng

John L. Ng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9009689
    Abstract: Methods to improve optimization of compilation are presented. In one embodiment, a method includes identifying one or more optimization speculations with respect to a code region and speculatively performing transformation on an intermediate representation of the code region in accordance with an optimization speculation. The method includes generating an advice message corresponding to the optimization speculation and displaying the advice message if the optimization speculation results in an improved compilation result.
    Type: Grant
    Filed: November 9, 2010
    Date of Patent: April 14, 2015
    Assignee: Intel Corporation
    Inventors: Rakesh Krishnaiyer, Hideki Saito Ido, Ernesto Su, John L. Ng, Jin Lin, Xinmin Tian, Robert Y. Geva
  • Patent number: 8793675
    Abstract: Methods and apparatus to provide loop parallelization based on loop splitting and/or index array are described. In one embodiment, one or more split loops, corresponding to an original loop, are generated based on the mis-speculation information. In another embodiment, a plurality of subloops are generated from an original loop based on an index array. Other embodiments are also described.
    Type: Grant
    Filed: December 24, 2010
    Date of Patent: July 29, 2014
    Assignee: Intel Corporation
    Inventors: Jin Lin, Nishkam Ravi, Xinmin Tian, John L. Ng, Renat V. Valiullin
  • Patent number: 8677338
    Abstract: Methods and apparatus to data dependence testing for loop fusion, e.g., with code replication, array contraction, and/or loop interchange, are described. In one embodiment, a compiler may optimize code for efficient execution during run-time by testing for dependencies associated with improving memory locality through code replication in loops that enable various loop transformations. Other embodiments are also described.
    Type: Grant
    Filed: June 4, 2008
    Date of Patent: March 18, 2014
    Assignee: Intel Corporation
    Inventors: John L. Ng, Rakesh Krishnaiyer, Alexander Y. Ostanevich
  • Patent number: 8589901
    Abstract: A system and method are configured to apply region level optimizations to a selected region of source code rather than loop level optimizations to a loop or loop nest. The region may include an outer loop, a plurality of inner loops and at least one control code. If the region includes an exceptional control flow statement and/or a procedure call, speculative region-level multi-versioning may be applied.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: November 19, 2013
    Inventors: Jin Lin, John L. Ng, Robert J. Cox, Xinmin Tian
  • Patent number: 8516468
    Abstract: In one embodiment of the invention, a method for fusing a first loop nested in a first IF statement with a second loop nested in a second IF statement without the use of modified and referenced (mod-ref) information to determine if certain conditional statements in the IF statements retain variable values.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: August 20, 2013
    Assignee: Intel Corporation
    Inventors: John L. Ng, Robert Cox, Dmitry V. Budanov
  • Patent number: 8453134
    Abstract: Provided are a method, system, and article of manufacture improving data locality and parallelism by code replication and array contraction. Source code including an array of elements referenced using at least two indices is processed. The array is nested within multiple loops, wherein at least two of the loops perform iterations with respect to the indices of the array, wherein the index incremented in at least one innermost loop of the loops does not comprise a leftmost index in the array. The source code is transformed to object code by performing operations including fusing at least two innermost loops of the loops in object code generated by compiling the source code by replicating statements from at least one of the innermost loops into a fused innermost loop and performing loop interchange in the object code to have the fused innermost loop provide iterations with respect to the leftmost index in the array.
    Type: Grant
    Filed: June 4, 2008
    Date of Patent: May 28, 2013
    Assignee: Intel Corporation
    Inventors: John L. Ng, Alexander Y. Ostanevich, Alexander L. Sushentsov
  • Publication number: 20120167069
    Abstract: Methods and apparatus to provide loop parallelization based on loop splitting and/or index array are described. In one embodiment, one or more split loops, corresponding to an original loop, are generated based on the mis-speculation information. In another embodiment, a plurality of subloops are generated from an original loop based on an index array. Other embodiments are also described.
    Type: Application
    Filed: December 24, 2010
    Publication date: June 28, 2012
    Inventors: Jin Lin, Nishkam Ravi, Xinmin Tian, John L. Ng, Renat V. Valiullin
  • Publication number: 20120167068
    Abstract: A system and method are configured to apply region level optimizations to a selected region of source code rather than loop level optimizations to a loop or loop nest. The region may include an outer loop, a plurality of inner loops and at least one control code. If the region includes an exceptional control flow statement and/or a procedure call, speculative region-level multi-versioning may be applied.
    Type: Application
    Filed: December 22, 2010
    Publication date: June 28, 2012
    Inventors: Jin Lin, John L. Ng, Robert J. Cox, Xinmin Tian
  • Publication number: 20120117552
    Abstract: Methods to improve optimization of compilation are presented. In one embodiment, a method includes identifying one or more optimization speculations with respect to a code region and speculatively performing transformation on an intermediate representation of the code region in accordance with an optimization speculation. The method includes generating an advice message corresponding to the optimization speculation and displaying the advice message if the optimization speculation results in an improved compilation result.
    Type: Application
    Filed: November 9, 2010
    Publication date: May 10, 2012
    Inventors: Rakesh Krishnaiyer, Hideki Saito Ido, Ernesto Su, John L. Ng, Jin Lin, Xinmin Tian, Robert Y. Geva
  • Publication number: 20090328021
    Abstract: In one embodiment of the invention, a method for fusing a first loop nested in a first IF statement with a second loop nested in a second IF statement without the use of modified and referenced (mod-ref) information to determine if certain conditional statements in the IF statements retain variable values.
    Type: Application
    Filed: June 30, 2008
    Publication date: December 31, 2009
    Inventors: John L. Ng, Robert Cox, Dmitry V. Budanov
  • Publication number: 20090307675
    Abstract: Methods and apparatus to data dependence testing for loop fusion, e.g., with code replication, array contraction, and/or loop interchange, are described. In one embodiment, a compiler may optimize code for efficient execution during run-time by testing for dependencies associated with improving memory locality through code replication in loops that enable various loop transformations. Other embodiments are also described.
    Type: Application
    Filed: June 4, 2008
    Publication date: December 10, 2009
    Inventors: John L. Ng, Rakesh Krishnaiyer, Alexander Y. Ostanevich
  • Publication number: 20090307674
    Abstract: Provided are a method, system, and article of manufacture improving data locality and parallelism by code replication and array contraction. Source code including an array of elements referenced using at least two indices is processed. The array is nested within multiple loops, wherein at least two of the loops perform iterations with respect to the indices of the array, wherein the index incremented in at least one innermost loop of the loops does not comprise a leftmost index in the array. The source code is transformed to object code by performing operations including fusing at least two innermost loops of the loops in object code generated by compiling the source code by replicating statements from at least one of the innermost loops into a fused innermost loop and performing loop interchange in the object code to have the fused innermost loop provide iterations with respect to the leftmost index in the array.
    Type: Application
    Filed: June 4, 2008
    Publication date: December 10, 2009
    Inventors: John L. NG, Alexander Y. OSTANEVICH, Alexander L. SUSHENTSOV
  • Patent number: 6880154
    Abstract: An apparatus, method, and program product for optimizing code that contains dynamically-allocated memory. The aliasing behavior of internal pointers of dynamically-allocated memory is used to disambiguate memory accesses and to eliminate false data dependencies. It is determined whether a dynamically-allocated array will behave like a statically-allocated array throughout the entire program execution once it has been allocated. This determination is used to improve the instruction scheduling efficiency, which yields better performance.
    Type: Grant
    Filed: June 29, 2001
    Date of Patent: April 12, 2005
    Assignee: Intel Corporation
    Inventors: Somnath Ghosh, Rakesh Krishnaiyer, Wei Li, Abhay Kanhere, Dattatraya Kulkarni, Chu-cheow Lim, John L. Ng
  • Publication number: 20030005420
    Abstract: An apparatus, method, and program product for optimizing code that contains dynamically-allocated memory. The aliasing behavior of internal pointers of dynamically-allocated memory is used to disambiguate memory accesses and to eliminate false data dependencies. It is determined whether a dynamically-allocated array will behave like a statically-allocated array throughout the entire program execution once it has been allocated. This determination is used to improve the instruction scheduling efficiency, which yields better performance.
    Type: Application
    Filed: June 29, 2001
    Publication date: January 2, 2003
    Inventors: Somnath Ghosh, Rakesh Krishnaiyer, Wei Li, Abhay Kanhere, Dattatraya Kulkarni, Chu-cheow Lim, John L. Ng
  • Patent number: 5485619
    Abstract: A subscript table mapping system for optimizing the compilation of certain Fortran 90 array construction and array manipulation transformation functions. The subscript table data object of this invention is used to perform the three compiler optimizations, including subscript dependency analysis, subscript table transformation and optimized code generation. Application of a simple subscript mapping function tailored to the particular intrinsic Fortran 90 array variable transformation function permits compilation of executable binary code that saves substantial processing steps and data storage space by avoiding during execution the usual requirement for temporary storage of abstract transformational array variables.
    Type: Grant
    Filed: December 29, 1993
    Date of Patent: January 16, 1996
    Assignee: International Business Machines Corporation
    Inventors: Michael Lai, John L. Ng, Jin-Fan Shaw