Patents by Inventor John L. Reid
John L. Reid has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9875102Abstract: Embodiments of the invention provide a method of creating, based on an operating-system-scheduled thread running on an operating-system-visible sequencer and using an instruction set extension, a persistent user-level thread to run on an operating-system-sequestered sequencer independently of context switch activities on the operating-system-scheduled thread. The operating-system-scheduled thread and the persistent user-level thread may share a common virtual address space. Embodiments of the invention may also provide a method of causing a service thread running on an additional operating-system-visible sequencer to provide operating system services to the persistent user-level thread. Embodiments of the invention may further provide apparatus, system, and machine-readable medium thereof.Type: GrantFiled: December 21, 2016Date of Patent: January 23, 2018Assignee: Intel CorporationInventors: Gautham Chinya, Hong Wang, Prashant Sethi, Shivnandan Kaushik, Bryant Bigbee, John Shen, Richard Hankins, Xiang Zou, Baiju V. Patel, Jason W. Brandt, Anil Aggarwal, John L. Reid
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Patent number: 9766891Abstract: Embodiments of the invention provide a method of creating, based on an operating-system-scheduled thread running on an operating-system-visible sequencer and using an instruction set extension, a persistent user-level thread to run on an operating-system-sequestered sequencer independently of context switch activities on the operating-system-scheduled thread. The operating-system-scheduled thread and the persistent user-level thread may share a common virtual address space. Embodiments of the invention may also provide a method of causing a service thread running on an additional operating-system-visible sequencer to provide operating system services to the persistent user-level thread. Embodiments of the invention may further provide apparatus, system, and machine-readable medium thereof.Type: GrantFiled: May 27, 2016Date of Patent: September 19, 2017Assignee: Intel CorporationInventors: Gautham Chinya, Hong Wang, Prashant Sethi, Shivnandan Kaushik, Bryant Bigbee, John Shen, Richard Hankins, Xiang Zou, Baiju V. Patel, Jason W. Brandt, Anil Aggarwal, John L. Reid
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Publication number: 20170102944Abstract: Embodiments of the invention provide a method of creating, based on an operating-system-scheduled thread running on an operating-system-visible sequencer and using an instruction set extension, a persistent user-level thread to run on an operating-system-sequestered sequencer independently of context switch activities on the operating-system-scheduled thread. The operating-system-scheduled thread and the persistent user-level thread may share a common virtual address space. Embodiments of the invention may also provide a method of causing a service thread running on an additional operating-system-visible sequencer to provide operating system services to the persistent user-level thread. Embodiments of the invention may further provide apparatus, system, and machine-readable medium thereof.Type: ApplicationFiled: December 21, 2016Publication date: April 13, 2017Inventors: Gautham Chinya, Hong Wang, Prashant Sethi, Shivnandan Kaushik, Bryant Bigbee, John Shen, Richard Hankins, Xiang Zou, Baiju V. Patel, Jason W. Brandt, Anil Aggarwal, John L. Reid
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Publication number: 20160274910Abstract: Embodiments of the invention provide a method of creating, based on an operating-system-scheduled thread running on an operating-system-visible sequencer and using an instruction set extension, a persistent user-level thread to run on an operating-system-sequestered sequencer independently of context switch activities on the operating-system-scheduled thread. The operating-system-scheduled thread and the persistent user-level thread may share a common virtual address space. Embodiments of the invention may also provide a method of causing a service thread running on an additional operating-system-visible sequencer to provide operating system services to the persistent user-level thread. Embodiments of the invention may further provide apparatus, system, and machine-readable medium thereof.Type: ApplicationFiled: May 27, 2016Publication date: September 22, 2016Inventors: Gautham Chinya, Hong Wang, Prashant Sethi, Shivnandan Kaushik, Bryant Bigbee, John Shen, Richard Hankins, Xiang Zou, Baiju V. Patel, Jason W. Brandt, Anil Aggarwal, John L. Reid
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Patent number: 9383997Abstract: Embodiments of the invention provide a method of creating, based on an operating-system-scheduled thread running on an operating-system-visible sequencer and using an instruction set extension, a persistent user-level thread to run on an operating-system-sequestered sequencer independently of context switch activities on the operating-system-scheduled thread. The operating-system-scheduled thread and the persistent user-level thread may share a common virtual address space. Embodiments of the invention may also provide a method of causing a service thread running on an additional operating-system-visible sequencer to provide operating system services to the persistent user-level thread. Embodiments of the invention may further provide apparatus, system, and machine-readable medium thereof.Type: GrantFiled: June 11, 2013Date of Patent: July 5, 2016Assignee: Intel CorporationInventors: Gautham Chinya, Hong Wang, Prashant Sethi, Shivnandan Kaushik, Bryant Bigbee, John Shen, Richard Hankins, Xiang Zou, Baiju V. Patel, Jason W. Brandt, Anil Aggarwal, John L. Reid
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Patent number: 8677163Abstract: Embodiments of an invention related to context state management based on processor features are disclosed. In one embodiment, a processor includes instruction logic and state management logic. The instruction logic is to receive a state management instruction having a parameter to identify a subset of the features supported by the processor. The state management logic is to perform a state management operation specified by the state management instruction.Type: GrantFiled: March 15, 2013Date of Patent: March 18, 2014Assignee: Intel CorporationInventors: Don Van Dyke, Michael Mishaeli, Ittai Anati, Baiju V. Patel, Will Deutsch, Rajesh R. Sha, Gilbert Neiger, James B. Crossland, Chris J. Newburn, Bryant E. Bigbee, Muhammad Faisal Azeem, John L. Reid, Dion Rodgers
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Patent number: 8631261Abstract: Embodiments of an invention related to context state management based on processor features are disclosed. In one embodiment, a processor includes instruction logic and state management logic. The instruction logic is to receive a state management instruction having a parameter to identify a subset of the features supported by the processor. The state management logic is to perform a state management operation specified by the state management instruction.Type: GrantFiled: December 31, 2007Date of Patent: January 14, 2014Assignee: Intel CorporationInventors: Don A. Van Dyke, Michael Mishaeli, Ittai Anati, Baiju V. Patel, Will Deutsch, Rajesh Shah, Gilbert Neiger, James B. Crossland, Chris J. Newburn, Bryant E. Bigbee, Muhammad Faisal Azeem, John L. Reid, Dion Rodgers
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Publication number: 20130275735Abstract: Embodiments of the invention provide a method of creating, based on an operating-system-scheduled thread running on an operating-system-visible sequencer and using an instruction set extension, a persistent user-level thread to run on an operating-system-sequestered sequencer independently of context switch activities on the operating-system-scheduled thread. The operating-system-scheduled thread and the persistent user-level thread may share a common virtual address space. Embodiments of the invention may also provide a method of causing a service thread running on an additional operating-system-visible sequencer to provide operating system services to the persistent user-level thread. Embodiments of the invention may further provide apparatus, system, and machine-readable medium thereof.Type: ApplicationFiled: June 11, 2013Publication date: October 17, 2013Inventors: Gautham Chinya, Hong Wang, Prashant Sethi, Shivnandan Kaushik, Bryant Bigbee, John Shen, Richard Hankins, Xiang Zou, Baiju V. Patel, Jason W. Brandt, Anil Aggarwal, John L. Reid
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Publication number: 20130219154Abstract: Embodiments of an invention related to context state management based on processor features are disclosed. In one embodiment, a processor includes instruction logic and state management logic. The instruction logic is to receive a state management instruction having a parameter to identify a subset of the features supported by the processor. The state management logic is to perform a state management operation specified by the state management instruction.Type: ApplicationFiled: March 15, 2013Publication date: August 22, 2013Inventors: Don A. Van Dyke, Michael Mishaeli, Ittai Anati, Baiju V. Patel, Will Deutsch, Rajesh Shah, Gilbert Neiger, James B. Crossland, Chris J. Newburn, Bryant E. Bigbee, Muhammad Faisal Azeem, John L. Reid, Dion Rodgers
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Patent number: 8516483Abstract: Operating system services are transparently triggered for thread execution resources (“sequencers”) that are sequestered from view of the operating system. A “surrogate” thread that is managed by, and visible to, the operating system is utilized to acquire OS services on behalf of a sequestered sequencer. Multi-shred contention for shred-specific resources may thus be alleviated. Other embodiments are also described and claimed.Type: GrantFiled: May 13, 2005Date of Patent: August 20, 2013Assignee: Intel CorporationInventors: Gautham Chinya, Hong Wang, Richard A. Hankins, Shivnandan D. Kaushik, Bryant Bigbee, John Shen, Prashant Sethi, Baiju V. Patel, John L. Reid
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Patent number: 8479217Abstract: Embodiments of the invention provide a method of creating, based on an operating-system-scheduled thread running on an operating-system-visible sequencer and using an instruction set extension, a persistent user-level thread to run on an operating-system-sequestered sequencer independently of context switch activities on the operating-system-scheduled thread. The operating-system-scheduled thread and the persistent user-level thread may share a common virtual address space. Embodiments of the invention may also provide a method of causing a service thread running on an additional operating-system-visible sequencer to provide operating system services to the persistent user-level thread. Embodiments of the invention may further provide apparatus, system, and machine-readable medium thereof.Type: GrantFiled: August 30, 2011Date of Patent: July 2, 2013Assignee: Intel CorporationInventors: Gautham Chinya, Hong Wang, Prashant Sethi, Shivnandan Kaushik, Bryant Bigbee, John Shen, Richard Hankins, Xiang Zou, Baiju V. Patel, Jason W. Brandt, Anil Aggarwal, John L. Reid
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Publication number: 20130042093Abstract: Embodiments of an invention related to context state management based on processor features are disclosed. In one embodiment, a processor includes instruction logic and state management logic. The instruction logic is to receive a state management instruction having a parameter to identify a subset of the features supported by the processor. The state management logic is to perform a state management operation specified by the state management instruction.Type: ApplicationFiled: December 31, 2007Publication date: February 14, 2013Inventors: Don A. Van Dyke, Michael Mishaeli, Ittai Anati, Baiju V. Patel, Will Deutsch, Rajesh Shah, Gilbert Neiger, James B. Crossland, Chris J. Newburn, Bryant E. Bigbee, Muhammad Faisal Azeem, John L. Reid, Dion Rodgers
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Publication number: 20110314480Abstract: Embodiments of the invention provide a method of creating, based on an operating-system-scheduled thread running on an operating-system-visible sequencer and using an instruction set extension, a persistent user-level thread to run on an operating-system-sequestered sequencer independently of context switch activities on the operating-system-scheduled thread. The operating-system-scheduled thread and the persistent user-level thread may share a common virtual address space. Embodiments of the invention may also provide a method of causing a service thread running on an additional operating-system-visible sequencer to provide operating system services to the persistent user-level thread. Embodiments of the invention may further provide apparatus, system, and machine-readable medium thereof.Type: ApplicationFiled: August 30, 2011Publication date: December 22, 2011Inventors: Gautham Chinya, Hong Wang, Prashant Sethi, Shivnandan Kaushik, Bryant Bigbee, John Shen, Richard Hankins, Zou Xiang, Baiju V. Patel, Jason W. Brandt, Anil Aggarwal, John L. Reid
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Patent number: 8028295Abstract: Embodiments of the invention provide a method of creating, based on an operating-system-scheduled thread running on an operating-system-visible sequencer and using an instruction set extension, a persistent user-level thread to run on an operating-system-sequestered sequencer independently of context switch activities on the operating-system-scheduled thread. The operating-system-scheduled thread and the persistent user-level thread may share a common virtual address space. Embodiments of the invention may also provide a method of causing a service thread running on an additional operating-system-visible sequencer to provide operating system services to the persistent user-level thread. Embodiments of the invention may further provide apparatus, system, and machine-readable medium thereof.Type: GrantFiled: September 30, 2005Date of Patent: September 27, 2011Assignee: Intel CorporationInventors: Gautham Chinya, Hong Wang, Prashant Sethi, Shivnandan Kaushik, Bryant Bigbee, John Shen, Richard Hankins, Xiang Zou, Baiju V. Patel, Jason W. Brandt, Anil Aggarwal, John L. Reid
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Patent number: 7810083Abstract: Method, apparatus and system embodiments to provide user-level creation, control and synchronization of OS-invisible “shreds” of execution via an abstraction layer for a system that includes one or more sequencers that are sequestered from operating system control. For at least one embodiment, the abstraction layer provides sequestration logic, proxy execution logic, transition detection and shred suspension logic, and sequencer arithmetic logic. Other embodiments are also described and claimed.Type: GrantFiled: December 30, 2004Date of Patent: October 5, 2010Assignee: Intel CorporationInventors: Gautham N. Chinya, Hong Wang, Xiang Zou, James Paul Held, Prashant Sethi, Trung Diep, Anil Aggarwal, Baiju V. Patel, Shiv Kaushik, Bryant Bigbee, John Shen, Richard A. Hankins, John L. Reid
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Patent number: 7743233Abstract: Disclosed are embodiments of a system, methods and mechanism for management and translation of mapping between logical sequencer addresses and physical or logical sequencers in a multi-sequencer multithreading system. A mapping manager may manage assignment and mapping of logical sequencer addresses or pages to actual sequencers or frames of the system. Rationing logic associated with the mapping manager may take into account sequencer attributes when such mapping is performed Relocation logic associated with the mapping manager may manage spill and fill of context information to/from a backing store when re-mapping actual sequencers. Sequencers may be allocated singly, or may be allocated as part of partitioned blocks. The mapping manager may also include translation logic that provides an identifier for the mapped sequencer each time a logical sequencer address is used in a user program. Other embodiments are also described and claimed.Type: GrantFiled: April 5, 2005Date of Patent: June 22, 2010Assignee: Intel CorporationInventors: Hong Wang, Gautham N. Chinya, Richard A. Hankins, Shivnandan D. Kaushik, Bryant Bigbee, John Shen, Per Hammarlund, Xiang Zou, Jason W. Brandt, Prashant Sethi, Douglas M. Carmean, Baiju V. Patel, Scott Dion Rodgers, Ryan N. Rakvic, John L. Reid, David K. Poulsen, Sanjiv M. Shah, James Paul Held, James Charles Abel
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Patent number: 7246135Abstract: Two applications running on the same or different processor-based systems may share a class. In some embodiments, the shared class may be shared out of shared memory. In addition, the object defined member data that is process specific may be duplicated in the address space of each program that uses the object.Type: GrantFiled: January 8, 2001Date of Patent: July 17, 2007Assignee: Intel CorporationInventor: John L. Reid
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Patent number: 6567016Abstract: A wireless keyboard may be provided with a guard protocol which prevents unintended typematics. An alive signal may be periodically generated to advise a host processor-based system that the keyboard communication link is still effective. If the host processor-based system receives a key make signal but does not receive a break signal or an alive signal, the processor-based system may deduce that the link has gone inactive, and may generate its own break signal. This avoids unnecessary power consumption and unnecessary typematics.Type: GrantFiled: December 3, 1999Date of Patent: May 20, 2003Assignee: Intel CorporationInventors: Krishnan Rajamani, Harley D. Johnson, Steven C. Lo, John L. Reid, Venkatakrishna U. Yellepeddy
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Patent number: 6511378Abstract: In one embodiment, an operating system may assign a product ID to the game controller that matches the product ID provided with or for the game controller.Type: GrantFiled: May 5, 2000Date of Patent: January 28, 2003Assignee: Intel CorporationInventors: Dhiraj Bhatt, Lynette A. Castlevetro, Wells A. Brimhall, Venkat U. Yellepeddy, John L. Reid
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Publication number: 20020091867Abstract: Two applications running on the same or different processor-based systems may share a class. In some embodiments, the shared class may be shared out of shared memory. In addition, the object defined member data that is process specific may be duplicated in the address space of each program that uses the object.Type: ApplicationFiled: January 8, 2001Publication date: July 11, 2002Inventor: John L. Reid