Abstract: Fuel oil compositions, and methods for blending such fuel oil compositions, to enhance initial compatibility and longer term stability when such fuel oil compositions are blended to meet IMO 2020 low sulfur fuel oil requirements (ISO 8217). In one or more embodiments, asphaltenic resid base stocks are blended with high aromatic slurry oil to facilitate initial compatibility such that low sulfur cutter stocks, e.g., vacuum gas oil and/or cycle oil, may be further blended therein to cut sulfur content while maintaining longer term stability. These fuel oil compositions are economically advantageous when used as marine low sulfur fuel oils because greater concentrations of high viscosity resids are present in the final blend.

Abstract: A cloud-based modeler component that generates interactive models of an industrial automation system(s) (IAS(s)) is presented. An interactive model facilitates remote viewing of, interaction with, troubleshooting of problems with, or optimization of industrial assets of an IAS. The modeler component polls industrial assets via cloud gateways to obtain information relating to the industrial assets to identify industrial assets of the IAS and relationships with other industrial assets or can receive information from a communication device that obtains information relating to legacy industrial assets to identify those legacy assets and their relationships. The modeler component generates an interactive model of the industrial assets of the IAS based on the information.

Abstract: A computer-implemented method includes executing one or more tests on a computing device. The computing device has Instruction Execution Protection (IEP), and each test of the one or more tests includes selectively setting one or more IEP bits of one or more page tables, where each IEP bit prevents code in a respective storage block from being executed. During the one or more tests, an IEP exception is detected, by a computer processor, each time an attempt is made to execute code in a storage block for which a respective IEP bit is set. Test results of the one or more tests are determined based on the detecting. A remedial action is performed in response to the test results of the one or more tests.

Abstract: A computer-implemented method includes executing one or more tests on a computing device. The computing device has Instruction Execution Protection (IEP), and each test of the one or more tests includes selectively setting one or more IEP bits of one or more page tables, where each IEP bit prevents code in a respective storage block from being executed. During the one or more tests, an IEP exception is detected, by a computer processor, each time an attempt is made to execute code in a storage block for which a respective IEP bit is set. Test results of the one or more tests are determined based on the detecting. A remedial action is performed in response to the test results of the one or more tests.

Abstract: A computer-implemented method includes executing one or more tests on a computing device. The computing device has Instruction Execution Protection (IEP), and each test of the one or more tests includes selectively setting one or more IEP bits of one or more page tables, where each IEP bit prevents code in a respective storage block from being executed. During the one or more tests, an IEP exception is detected, by a computer processor, each time an attempt is made to execute code in a storage block for which a respective IEP bit is set. Test results of the one or more tests are determined based on the detecting. A remedial action is performed in response to the test results of the one or more tests.

Abstract: A computer-implemented method includes executing one or more tests on a computing device. The computing device has Instruction Execution Protection (IEP), and each test of the one or more tests includes selectively setting one or more IEP bits of one or more page tables, where each IEP bit prevents code in a respective storage block from being executed. During the one or more tests, an IEP exception is detected, by a computer processor, each time an attempt is made to execute code in a storage block for which a respective IEP bit is set. Test results of the one or more tests are determined based on the detecting. A remedial action is performed in response to the test results of the one or more tests.

Abstract: An aspect includes include selective purging of entries from translation look-aside buffers (TLBs). A method includes building multiple logical systems in a computing environment, the multiple logical systems including at least two level-two guests. TLB entries are created in a TLB for the level-two guests by executing fetch and store instructions. A subset of the TLB entries is purged in response to a selective TLB purge instruction, the subset including TLB entries created for a first one of the level-two guests. Subsequent to the purging, verifying that the subset of the TLB entries were purged from the TLB, and determining whether a second one of the level-two guests is operational, the determining including executing at least one instruction that accesses a TLB entry of the second one of the level-two guests. Test results are generated based on the verifying and the determining. The test results are output.

Abstract: A pin tumbler lock of a first embodiment includes a shell containing top pins; and a plug, rotatable within the shell, containing standard bottom pins, and a shorter bottom pin, set back from the face of the plug. A tubular key has bitings corresponding to the standard bottom pins, and a projection corresponding to the short bottom pin. When the key is inserted, the bitings and the projection press all the bottom pins to the shear line. In a second embodiment, a lock includes a shell containing top pins and a depression; and a plug, rotatable within the shell, containing bottom pins. The depression is configured and dimensioned to receive one of the bottom pins. The depression may be opposite one of the bottom pins, and there may be one more bottom pin than top pins. When the key is inserted, the bottom pins are moved to the shear line.