Patents by Inventor John L. Weber

John L. Weber has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10521594
    Abstract: A computer-implemented method includes executing one or more tests on a computing device. The computing device has Instruction Execution Protection (IEP), and each test of the one or more tests includes selectively setting one or more IEP bits of one or more page tables, where each IEP bit prevents code in a respective storage block from being executed. During the one or more tests, an IEP exception is detected, by a computer processor, each time an attempt is made to execute code in a storage block for which a respective IEP bit is set. Test results of the one or more tests are determined based on the detecting. A remedial action is performed in response to the test results of the one or more tests.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: December 31, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ali Y. Duale, Shailesh R. Gami, John L. Weber, Dennis Wittig
  • Publication number: 20190171824
    Abstract: A computer-implemented method includes executing one or more tests on a computing device. The computing device has Instruction Execution Protection (IEP), and each test of the one or more tests includes selectively setting one or more IEP bits of one or more page tables, where each IEP bit prevents code in a respective storage block from being executed. During the one or more tests, an IEP exception is detected, by a computer processor, each time an attempt is made to execute code in a storage block for which a respective IEP bit is set. Test results of the one or more tests are determined based on the detecting. A remedial action is performed in response to the test results of the one or more tests.
    Type: Application
    Filed: February 8, 2019
    Publication date: June 6, 2019
    Inventors: ALI Y. DUALE, SHAILESH R. GAMI, JOHN L. WEBER, DENNIS WITTIG
  • Patent number: 10262144
    Abstract: A computer-implemented method includes executing one or more tests on a computing device. The computing device has Instruction Execution Protection (IEP), and each test of the one or more tests includes selectively setting one or more IEP bits of one or more page tables, where each IEP bit prevents code in a respective storage block from being executed. During the one or more tests, an IEP exception is detected, by a computer processor, each time an attempt is made to execute code in a storage block for which a respective IEP bit is set. Test results of the one or more tests are determined based on the detecting. A remedial action is performed in response to the test results of the one or more tests.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: April 16, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ali Y. Duale, Shailesh R. Gami, John L. Weber, Dennis Wittig
  • Publication number: 20180173880
    Abstract: A computer-implemented method includes executing one or more tests on a computing device. The computing device has Instruction Execution Protection (IEP), and each test of the one or more tests includes selectively setting one or more IEP bits of one or more page tables, where each IEP bit prevents code in a respective storage block from being executed. During the one or more tests, an IEP exception is detected, by a computer processor, each time an attempt is made to execute code in a storage block for which a respective IEP bit is set. Test results of the one or more tests are determined based on the detecting. A remedial action is performed in response to the test results of the one or more tests.
    Type: Application
    Filed: December 15, 2016
    Publication date: June 21, 2018
    Inventors: Ali Y. Duale, Shailesh R. Gami, John L. Weber, Dennis Wittig
  • Patent number: 9798597
    Abstract: An aspect includes include selective purging of entries from translation look-aside buffers (TLBs). A method includes building multiple logical systems in a computing environment, the multiple logical systems including at least two level-two guests. TLB entries are created in a TLB for the level-two guests by executing fetch and store instructions. A subset of the TLB entries is purged in response to a selective TLB purge instruction, the subset including TLB entries created for a first one of the level-two guests. Subsequent to the purging, verifying that the subset of the TLB entries were purged from the TLB, and determining whether a second one of the level-two guests is operational, the determining including executing at least one instruction that accesses a TLB entry of the second one of the level-two guests. Test results are generated based on the verifying and the determining. The test results are output.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: October 24, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ali Y. Duale, Shailesh R. Gami, John L. Weber, Dennis W Wittig
  • Patent number: 7441431
    Abstract: A pin tumbler lock of a first embodiment includes a shell containing top pins; and a plug, rotatable within the shell, containing standard bottom pins, and a shorter bottom pin, set back from the face of the plug. A tubular key has bitings corresponding to the standard bottom pins, and a projection corresponding to the short bottom pin. When the key is inserted, the bitings and the projection press all the bottom pins to the shear line. In a second embodiment, a lock includes a shell containing top pins and a depression; and a plug, rotatable within the shell, containing bottom pins. The depression is configured and dimensioned to receive one of the bottom pins. The depression may be opposite one of the bottom pins, and there may be one more bottom pin than top pins. When the key is inserted, the bottom pins are moved to the shear line.
    Type: Grant
    Filed: January 9, 2007
    Date of Patent: October 28, 2008
    Assignee: Micro Security Devices, Inc.
    Inventors: John L. Weber, Marc W. Tobias, George Yu