Patents by Inventor John L. Worst

John L. Worst has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 3986091
    Abstract: An apparatus for positioning a carrier means along a line of print in either of two directions. The carrier means is positioned by a D.C. motor which is driven by a pair of current driver circuits, one of which controls the flow of drive current in a forward direction and the other of which controls the flow of current in the reverse direction. The motor is capable of driving the carrier means at a first predetermined high speed when it is determined that the desired destination carrier position is more than a predetermined number of carrier positions from the present carrier position and at a second predetermined low speed when the desired destination carrier position is less than or equal to a predetermined number of carrier positions from the present carrier position. An electronic tachometer means operates to maintain a relatively constant speed while operating in the predetermined high speed state and while operating in the predetermined low speed state.
    Type: Grant
    Filed: November 15, 1974
    Date of Patent: October 12, 1976
    Assignee: Burroughs Corporation
    Inventors: Virgilio J. Quiogue, Cornelius Eldert, John L. Worst
  • Patent number: 3986094
    Abstract: A logic system for controlled energization of predetermined stepper motor phases for various optimal times employing a read only memory having a plurality of memory element arrays corresponding to predetermined stepper motor sequencing commands corresponding to all possible tilt position change attempts for a print head. The memory element arrays are addressed by a shift register which stores data representative of the previous print head tilt position and the destined print head tilt position as provided by a two bit latch. The addressed memory element array is sequenced by a counter incrementing the read only memory address provided by the shift register at various predetermined optimal time intervals provided by a timer which is preset by individual preset values stored in the memory element now being addressed.
    Type: Grant
    Filed: July 1, 1974
    Date of Patent: October 12, 1976
    Assignee: Burroughs Corporation
    Inventors: Virgilio J. Quioque, Cornelius Eldert, John L. Worst