Abstract: A system for determining a data converter operating mode includes measurement circuitry that measures a master clock frequency of a master clock signal received without a modification in frequency from a master clock signal source and that measures a frequency ratio between a frequency of a data clock signal and the master clock frequency. A mapping system maps the measurements of the master clock frequency and the frequency ratio to an operating mode of the data converter. In other embodiments, mapping systems map the measurements of the master clock frequency and the frequency ratio to an operating mode of the data converter based on mode priority constraints. In additional embodiments, mapping systems map the measurements of the master clock frequency and the frequency ratio to an operating mode of the data converter by narrowing the choices of master clock divide ratios and subsequently determining an operating mode from the frequency ratio.

Abstract: Methods and Apparatuses are provided for automatically converting a word length of sample data being transmitted over a serial link. A serial interface transmits and/or receives one or more data words comprising digital signals, a bit clock synchronizes transmission of individual bits, and a word clock is used to group the bits into sample words. A desired word length is determined based on the relationship between the bit clock and the word clock during the transmission or reception of a data word. Based on the desired word length, the sample data is either truncated or padded, and an appropriate amount of dither is added to the sample words to reduce the distortion and quantization artifacts introduced by the word length conversion.

Abstract: A pulse width modulation circuit for driving a full-bridge output load includes a pulse width modulation stage for generating, from an input data stream, a pulse width modulated data stream for driving a terminal of a full-bridge output load and another pulse width modulated data stream for driving another terminal of the full bridge output load. A delay circuit delays the another pulse width modulated data stream relative to the pulse width modulated data stream such that edges of the another pulse width modulated data stream and edges of the pulse width modulated data stream are temporally spaced.

Abstract: A system for determining a data converter operating mode includes measurement circuitry for measuring master clock frequency of a master clock signal and a frequency ratio between a frequency of a data clock signal and the master clock frequency and a mapping system for mapping the measurement of the frequency ratio to an operating mode of the data converter. The mapping system generates a set of candidate divide ratios for dividing the master clock frequency to generate corresponding internal master clock frequencies of an internal clock signal and determines the lowest divide ratio which generates a supported internal master clock frequency. In an alternate embodiment, the mapping system determines the divide ratio required by a filter of the data converter by dividing the data clock to master clock frequency ratio by a data clock to internal clock frequency ratio between the data clock frequency and the frequency of an internal clock signal.

Abstract: A system for determining a data converter operating mode includes measurement circuitry which measures a master clock frequency, measures a frequency ratio between a frequency of a data clock signal and the master clock frequency, and measures a selected operating condition of the data converter. A mapping system maps the measurements of the master clock frequency, the frequency ratio, and the selected operating condition, to an operating mode of the data converter. In another embodiment, the measurement circuitry adjusts the measurement of the master clock frequency in response to a measurement of the operating conditions of the data converter. In a further embodiment, user input information varies the measurement of the master clock frequency.

Abstract: A noise shaping system including an inner loop and outer noise shaping loops. The inner noise shaping loop includes an inner loop filter and a quantizer for quantizing an output of the inner loop filter. The outer noise shaping loop includes an outer loop filter having an input receiving feedback from the quantizer of the inner noise shaping loop and an output driving an input of the inner loop filter of the inner noise shaping loop.

Abstract: A method of generating a pulse width modulated data stream includes providing a first clock signal having a first frequency and selecting a divisor from a set of divisors for dividing the first frequency to select a pattern rate of a pulse width modulated data stream and thereby shift in frequency noise generated at the pattern rate during pulse width modulation. The first frequency of the first signal is divided to generate a second signal at the selected pattern rate. Noise shaping and requantizing is performed on the second signal to generate a noise shaped and requantized second signal and the pulse width modulated data stream having patterns at the selected pattern rate is generated in response to the first signal and the noise shaped and requantized second signal.

Abstract: A method of processing a digital data stream in a digital processing system includes filtering the digital data stream being processed through a delta-sigma modulator having a selected signal transfer function passing a frequency band of interest.

Abstract: A data converter including a digital volume control for continuously scaling a received stream of digital audio data by a selected factor and a low noise delta-sigma modulator for re-quantizing a scaled digital data stream output from the digital volume control.

Abstract: A method of amplitude control in a 1-bit digital system includes the step of scaling the stream of 1-bit data by a scaling factor corresponding to a selected output amplitude. The scaled data is modulated and the resulting modulated, scaled data is converted from digital to analog form.

Abstract: A method of sampling an input signal in a delta-sigma modulator having at least an integrator stage and a feedback digital-to-analog converter (DAC) stage includes sampling an input signal at a sampling rate by alternately utilizing the two sampling capacitors during two sampling cycles such that the two sampling capacitors are each being utilized at half the rate of the sampling rate. Samples from the two sampling capacitors are summed at the sampling rate at an intermediate node with a feedback samples provided by the feedback DAC stage at the sampling rate to generate output samples which are output from integrator stage at the sampling rate.

Abstract: A gain or input volume controller and method includes a modified R2R ladder network having a number of R2R branches, switches coupled respectively to the R2R branches, and a switch controller for respectively controlling the switches to control and provide an overall gain value for a signal. The switch controller further includes a mapper for mapping a gain control signal to the switches wherein the gain control signal respectively activates or deactivates the switches. A fine gain control stage provides a fine gain control of the overall gain value. A coarse gain control stage is coupled to the fine gain control stage. The coarse gain control stage includes the modified R2R ladder network and provides a coarse gain control of the overall gain value.

Abstract: A method of controlling noise in a pulse width modulation circuit includes varying a sample frequency and a range of information levels, wherein each sample within a data sample stream at the sample frequency represents a level within the range of information levels, to shift in frequency noise generated at the sample frequency during encoding of the data sample stream into pulse width modulated patterns.

Abstract: A feedback noise-shaper of an order of at least three implements a first pole set defining a signal transfer function of a selected corner frequency and a second pole set having at least one pole at a frequency at least twice the selected corner frequency defining a noise transfer function.

Abstract: A delta-sigma modulator of an order of at least three having a signal transfer function defining a signal low-pass response, the signal transfer function has a numerator and a denominator, the denominator defined by a product of first and second functions defining respective first and second pole sets such that a roll-off frequency of a low-pass response defined by the first pole set is at least twice a roll-off frequency of a low-pass response defined by the second pole set. The delta-sigma modulator also has a noise transfer function defining a noise high-pass response, the noise transfer function having a numerator and a denominator, the denominator defined by the product of the first and second functions. The numerator of the noise transfer function differs from the numerator of the signal transfer function and characterizes the noise high-pass response.

Abstract: A sample and hold circuit including a sampling capacitor for storing a sample of an input signal, an output stage for outputting the sample stored on the sampling capacitor; and input circuitry for sampling the input signal and storing the sample on the sampling capacitor. The input circuitry includes an autozeroing input buffer which selectively samples the input signal during a first operating phase and holds a sample of the input signal during a second operating phase. The autozeroing input buffer cancels any offset error. The input circuitry also includes switching circuitry for selectively coupling the sampling capacitor with an input of the sample and hold circuitry during the second operating phase and to an output of the autozeroing input buffer during the first operating phase.

Abstract: A method of processing digital audio data includes receiving an input stream of audio data having a first quantization and a high oversampling rate. The input stream is requantized in a first processing block at the high oversampling rate to a second quantization. The requantized stream of audio data is processed in a second processing block at the high oversampling rate and the second quantization.

Abstract: A system for determining a data converter operating mode includes measurement circuitry operable to measure a master clock frequency of a master clock signal and measure a frequency ratio between a data clock frequency of a data clock signal and the master clock frequency. A mapping system maps the measurements of the master clock frequency and the frequency ratio to an operating mode of the data converter utilizing an explicit formula. In a further embodiment, the mapping system maps the measurements of the master clock frequency and the frequency ratio to an operating mode of the data converter utilizing a lookup table. In an additional embodiment, the mapping system tests an available set of operating modes, independent of any previous tests, to determine a suitable operating mode for the data converter.

Abstract: A charge pump including a differential pair of transistors for controlling a current at a charge pump output node and a replica bias generator for selectively driving a first transistor of the differential pair of transistors into a fully-on state and a second transistor of the differential pair of transistors into a weak inversion state.

Abstract: A system for determining a data converter operating mode including measurement circuitry operable to measure a master clock frequency by comparing a frequency of a master clock signal and a frequency of a fixed frequency clock signal and operable to measure a frequency ratio between a frequency of a data clock signal and the master clock frequency. A mapping system maps the measurements of the master clock frequency and the frequency ratio to an operating mode of the data converter. In one particular embodiment, the fixed frequency clock signal is provided by an oscillator. In a further embodiment, the master clock signal is generated by multiplying the frequency of another clock signal.