Abstract: A CMOS analog integrated circuit comprising a plurality of nodes for simultaneously computing the largest of the signals at inputs of the nodes. There is a common line supplying current and producing a maximum voltage potential and a plurality of nodes connected to the common line. Each node comprises a follower transistor having a source operably connected to the common line for sourcing current and a gate being the input of the node and being connected to a current signal input source providing a current signal to the node to be compared to the current signals at respective ones of the other nodes. There is an inhibitor transistor having a gate connected to the common line and a drain operably connected to the gate of the follower transistor. The inhibitor transistor provides the voltage output of the node and inhibits the voltage output at all nodes connected to the common line which have a current signal which is smaller than the largest current signal connected to one of the nodes.