Patents by Inventor John Leidel

John Leidel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Stacked memory device system interconnect directory-based cache coherence methodology
    Patent number: 11741012
    Abstract: A system includes a plurality of host processors and a plurality of hybrid memory cube (HMC) devices configured as a distributed shared memory for the host processors. An HMC device includes a plurality of integrated circuit memory die including at least a first memory die arranged on top of a second memory die, and at least a portion of the memory of the memory die is mapped to include at least a portion of a memory coherence directory; and a logic base die including at least one memory controller configured to manage three-dimensional (3D) access to memory of the plurality of memory die by at least one second device, and logic circuitry configured to implement a memory coherence protocol for data stored in the memory of the plurality of memory die.
    Type: Grant
    Filed: October 8, 2020
    Date of Patent: August 29, 2023
    Assignee: Micron Technology, Inc.
    Inventors: John Leidel, Richard C Murphy
  • STACKED MEMORY DEVICE SYSTEM INTERCONNECT DIRECTORY-BASED CACHE COHERENCE METHODOLOGY
    Publication number: 20210034524
    Abstract: A system includes a plurality of host processors and a plurality of hybrid memory cube (HMC) devices configured as a distributed shared memory for the host processors. An HMC device includes a plurality of integrated circuit memory die including at least a first memory die arranged on top of a second memory die, and at least a portion of the memory of the memory die is mapped to include at least a portion of a memory coherence directory; and a logic base die including at least one memory controller configured to manage three-dimensional (3D) access to memory of the plurality of memory die by at least one second device, and logic circuitry configured to implement a memory coherence protocol for data stored in the memory of the plurality of memory die.
    Type: Application
    Filed: October 8, 2020
    Publication date: February 4, 2021
    Inventors: John Leidel, Richard C. Murphy
  • Stacked memory device system interconnect directory-based cache coherence methodology
    Patent number: 10838865
    Abstract: A system includes a plurality of host processors and a plurality of hybrid memory cube (HMC) devices configured as a distributed shared memory for the host processors. An HMC device includes a plurality of integrated circuit memory die including at least a first memory die arranged on top of a second memory die, and at least a portion of the memory of the memory die is mapped to include at least a portion of a memory coherence directory; and a logic base die including at least one memory controller configured to manage three-dimensional (3D) access to memory of the plurality of memory die by at least one second device, and logic circuitry configured to implement a memory coherence protocol for data stored in the memory of the plurality of memory die.
    Type: Grant
    Filed: May 7, 2015
    Date of Patent: November 17, 2020
    Assignee: Micron Technology, Inc.
    Inventors: John Leidel, Richard C Murphy
  • HYBRID MEMORY CUBE SYSTEM INTERCONNECT DIRECTORY-BASED CACHE COHERENCE METHODOLOGY
    Publication number: 20150324290
    Abstract: A system includes a plurality of host processors and a plurality of hybrid memory cube (HMC) devices configured as a distributed shared memory for the host processors. An HMC device includes a plurality of integrated circuit memory die including at least a first memory die arranged on top of a second memory die, and at least a portion of the memory of the memory die is mapped to include at least a portion of a memory coherence directory; and a logic base die including at least one memory controller configured to manage three-dimensional (3D) access to memory of the plurality of memory die by at least one second device, and logic circuitry configured to implement a memory coherence protocol for data stored in the memory of the plurality of memory die.
    Type: Application
    Filed: May 7, 2015
    Publication date: November 12, 2015
    Inventors: John Leidel, Richard C. Murphy