Patents by Inventor John Leonard Walters

John Leonard Walters has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5841195
    Abstract: A method is provided for forming contact via in an integrated circuit. Initially, a first buffer layer is formed over an insulating layer in an integrated circuit. The first buffer layer has a different etch rate from the insulating layer. A second buffer layer is then formed over the first buffer layer, with the second buffer layer having an etch rate which is faster than the first buffer layer. An isotropic etch is performed to create an opening through the second buffer layer and a portion of the first buffer layer. Because the second buffer layer etches faster than the first buffer layer, the slant of the sideswalls of the opening can be controlled. An anisotropic etch is then performed to complete formation of the contact via.
    Type: Grant
    Filed: May 24, 1995
    Date of Patent: November 24, 1998
    Assignee: STMicroelectronics, Inc.
    Inventors: Yih-Shung Lin, Lun-Tseng Lu, Fu-Tai Liou, Che-Chia Wei, John Leonard Walters
  • Patent number: 5670424
    Abstract: An interconnect structure, and method for forming same, is suitable for use in integrated circuits such as SRAM devices. The structure uses masking of a polycrystalline silicon interconnect level to move a P-N junction to a region within a polycrystalline silicon interconnect line, rather than at the substrate. This P-N junction can then be shorted out using a refractory metal silicide formed on the polycrystalline silicon interconnect structure.
    Type: Grant
    Filed: October 13, 1995
    Date of Patent: September 23, 1997
    Assignee: SGS-Thomson Microelectronics, Inc.
    Inventors: Tsiu Chiu Chan, Frank Randolph Bryant, John Leonard Walters