Abstract: A system for limiting the size of a local storage of a processor is provided. A facility is provided in association with a processor for setting a local storage size limit. This facility is a privileged facility and can only be accessed by the operating system running on a control processor in the multiprocessor system or the associated processor itself. The operating system sets the value stored in the local storage limit register when the operating system initializes a context switch in the processor. When the processor accesses the local storage using a request address, the local storage address corresponding to the request address is compared against the local storage limit size value in order to determine if the local storage address, or a modulo of the local storage address, is used to access the local storage.

Abstract: A system for limiting the size of a local storage of a processor is provided. A facility is provided in association with a processor for setting a local storage size limit. This facility is a privileged facility and can only be accessed by the operating system running on a control processor in the multiprocessor system or the associated processor itself. The operating system sets the value stored in the local storage limit register when the operating system initializes a context switch in the processor. When the processor accesses the local storage using a request address, the local storage address corresponding to the request address is compared against the local storage limit size value in order to determine if the local storage address, or a modulo of the local storage address, is used to access the local storage.

Abstract: A method for limiting the size of a local storage of a processor is provided. A facility is provided in association with a processor for setting a local storage size limit. This facility is a privileged facility and can only be accessed by the operating system running on a control processor in the multiprocessor system or the associated processor itself The operating system sets the value stored in the local storage limit register when the operating system initializes a context switch in the processor. When the processor accesses the local storage using a request address, the local storage address corresponding to the request address is compared against the 1ocal storage limit size value in order to determine if the local storage address, or a modulo of the local storage address, is used to access the local storage.

Abstract: A processor system is disclosed that integrates error correcting code (ECC) detection and correction hardware within an memory management circuit. ECC hardware circuitry provides detection, correction and generation of ECC data bits in conjunction with memory data read and writes. The disclosed methodology permits the detection and correction of soft single bit errors read from local memory in-line while using read modify write DMA circuit logic to correct local memory data. The disclosed methodology provides local memory data error detection and correction in a background memory scrub process without the need for additional in-line data logic.

Abstract: A system and method for verifying configuration data for configuring a microprocessor or system-on-a-chip (SoC) are provided. With the system and method, during initialization, configuration data is shifted into the microprocessor or SoC through a configuration input. The configuration data is shifted to all of the on-chip processor units to provide initial settings for configuration latches in the design. While the configuration data is being shifted to the on-chip processor units, a copy of the configuration data is also stored in a local storage of a test control unit. A private interface is provided between the test control unit and the processor units. Via the private interface, a processor unit receives the current configuration data for the processor units. The current configuration data is compared against the original configuration data stored in the test control unit to verify the current configuration of the processor units.

Abstract: A system and method for communicating with a processor event facility are provided. The system and method make use of a channel interface as the primary mechanism for communicating with the processor event facility. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.

Abstract: A method and apparatus is provided for testing the logic functionality and electrical continuity of a ring oscillator comprising an odd number of inverters connected to form a closed loop. In the method and apparatus, a known value is forced through the ring oscillator, to test the complete circuit path thereof. Thus, a low overhead deterministic test of the functionality of the ring oscillator is provided. In a useful embodiment of the invention, a method is provided for testing functionality and electrical continuity in a ring oscillator, wherein a first test device is inserted between the input of a first inverter and the output of an adjacent second inverter. The first test device is then operated to apply first and second test bits as input test signals to the first inverter input.

Abstract: A random number generator, a method, and a computer program product are provided for producing a random number seed. Each oscillator within an array of oscillators operates at a different frequency. The operating frequencies of each oscillator are not harmonically related, such that no integer multiple exists between the frequencies of any two oscillators. In one embodiment, the outputs of the array of oscillators connect to a multiple input latch. The multiple input latch also receives a sample signal, which is a clock signal. The clock signal samples the outputs of the array of oscillators, and the multiple input latch in conjunction with the random number determination logic (“RNDL”) produces a digital output (0 or 1) for each oscillator within the array. The RNDL uses these digital outputs to create a random number seed.

Abstract: A system and method for communicating instructions and data between a processor and external devices are provided. The system and method make use of a channel interface as the primary mechanism for communicating between the processor and a memory flow controller. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.

Abstract: A system and method for limiting the size of a local storage of a processor are provided. A facility is provided in association with a processor for setting a local storage size limit. This facility is a privileged facility and can only be accessed by the operating system running on a control processor in the multiprocessor system or the associated processor itself. The operating system sets the value stored in the local storage limit register when the operating system initializes a context switch in the processor. When the processor accesses the local storage using a request address, the local storage address corresponding to the request address is compared against the local storage limit size value in order to determine if the local storage address, or a modulo of the local storage address, is used to access the local storage.

Abstract: A circuit topology which can be used to create an array of individually tuned oscillators operating at different frequencies determined by common control inputs and an easily managed variation in design dimensions of several components is provided. An array of oscillators are provided arranged in columns and rows. Each oscillator in a column is unique from the other oscillators in the column based on number of stages in the oscillator and fanout so that each oscillator will operate at a unique frequency. Oscillators of different columns within the array may differ by a common setting of the selects to these oscillators and the physical ordering of the oscillators in the column to further reduce the possibility of injection locking. A base delay cell provides selects to each column of oscillators such that each column may be programmed to operate at a different frequency from its neighbors.

Abstract: In the present invention, register values are obtained by scanning, and are then written to one or more trace arrays on the chip. The scan data in the trace arrays is then read out by software. The register scan data can be recirculated among the registers, and addition scans can then be performed and written to the one or more trace arrays.

Abstract: The present invention provides for the hardware on-chip capturing and storage of performance count data about software programs running on the chip. Counters generate performance data about the programs, and the values of the counters are stored in a trace array. In an embodiment, instruction addresses and other data can be written along with the performance count data. In an embodiment, the data can be may be buffered and streamed to an external memory or device. In an embodiment, interval counters control the writing of the performance count data to the trace array.

Abstract: The present invention provides for authenticating code and/or data and providing a protected environment for execution. The present invention provides for dynamically partitioning and un-partitioning a local store for the authentication of code or data. The local store is partitioned into an isolated and non-isolated section. Code or data is loaded into the isolated section. The code or data is authenticated in the isolated section of the local store. After authentication, the code is executed. After execution, the memory within the isolated region of the attached processor unit is erased, and the attached processor unit de-partitions the isolated section within the local store.

Abstract: A method and an apparatus for generating a plurality of parameters of an object in a field of view is disclosed. An electrical image of the field of view is formed. The electrical image is processed to form a plurality of different representations of the electrical image where each different representation is a representation of a different parameter of the field of view. The positional information, which represents the boundary of the object, is generated. In response to the positional information that represents the boundary of the object being generated, corresponding locations in each of the different representations is traced. The different parameters from each of the different represents are calculated as the locations are traced in each of the different representations.

Abstract: A method and an apparatus for generating a plurality of parameters of an object in a field of view is disclosed. An electrical image of the field of view is formed. The electrical image is processed to form a plurality of different representations of the electrical image where each different representation is a representation of a different parameter of the field of view. The positional information, which represents the boundary of the object, is generated. In response to the positional information that represents the boundary of the object being generated, corresponding locations in each of the different representations is traced. The different parameters from each of the different represents are calculated as the locations are traced in each of the different representations.

Abstract: A system for recording and retrieval of data consisting of a data storage means having a pre-recorded signal imposed thereon, data recording and playback means, and a control means. The control means is coupled to the recording and playback means so that it receives the pre-recorded signal and controls the rate at which data is recorded on and recovered from the data storage means with respect to the pre-recorded signal.