Abstract: A bottom garment for providing improved appearance to the wearer. The garment includes a front panel; a back panel; and at least one tummy control panel formed of a low-stretch, high pre-tensioned fabric attached to the inside of the front panel beneath the waistband of the front panel. In one embodiment, the low-stretch, high pre-tension fabric is formed of a mesh construction. The front panel may further include at least one pocket assembly.

Abstract: A home security and control system for monitoring and controlling an external environment such as a home environment comprising: an Internet browser connectable to an extranet; an extranet located external to the home environment and accessible via the Internet browser; a communications server located in the extranet and adapted to interconnect on demand with one of a series of connection gateways located in predetermined home environments; and a connection gateway located in the home environment adapted to control and/or monitor the operation of at least one security device in the home environment; wherein upon accessing a predetermined address by the Internet browser on the extranet, the communications server connects to a predetermined one of the connection gateways to control and/or monitor the operation of the security device. The extranet can ideally be implemented as a Virtual Private Network (VPN) across an Internet substrate.

Abstract: An article having an improved closure device. The article includes an opening including: (i) an overlapping portion with a receiving aperture; and (ii) an underlying surface; and (b) an asymmetrically offset fastener attached to the underlying surface of the article for fastening the underlying surface to the overlapping portion, wherein the asymmetrically offset fastener is dimensionally greater in one direction than in the other direction with respect to the aperture.

Abstract: Disclosed is a computer processor (300) comprising a plurality of processing units (FU_n) and communication means (302) by which the plurality of processing units are interconnected. The communication means is dynamically configurable based on a computer program to be processed such that the processing units can selectively be arranged in at least first and second distinct configurations. The first distinct configuration (eg. FIG. 5) has a larger number of the processing units arranged in parallel than the second distinct configuration (eg. FIG. 6), and the second distinct configuration has a deeper pipeline depth than the first distinct configuration.

Abstract: A method for performing an Inverse Discrete Wavelet Transform is disclosed. The method comprises inverse transforming, using filters (706–710) having specified filter widths, data from associated sub-bands in a first sub-band level, to form processed data in a corresponding sub-band in the second sub-band level. The method further inverse transforms, in a pipeline fashion, using second filters (712–716) having the same corresponding associated filter widths, the processed data in conjunction with corresponding data from associated sub-bands in the second sub-band level.

Abstract: A method (40) and apparatus (30) is described for performing image rendering of high resolution computer generated images using limited memory and constrained rendering architectures. An image is segmented into a plurality of tiles (110). A graphics renderer (17), which is usually used for rendering low resolution images onto a display device (19), is used to render one tile (110) at a time. The rendered tile images are combined to form a band of the image (101) and the image data of the band (101) is transferred to a printer engine (20) for printing. Each band (101) is rendered and transferred to the printer engine (20) until the whole image is printed.

Abstract: A method of selecting transform segments from a data stream (426), the stream comprising a plurality of blocks each comprising a plurality of transform segments, is disclosed. The selection reorders the transform segments in a block, and comprises, for each said block, steps of selecting a first set of transform segments (426-432) suitable for direct inverse transformation to form a first data segment, selecting a second transform segment (1612) which is directly inverse transformable given availability of the first set (426-432), identifying a third transform segment (1608, 1610) which is not directly inverse transformable given availability of the first set (426-432) and the second transform segment (1612), and selecting a fourth transform segment (1610, 1608) which is required to support direct inverse transformation of the third transform segment (1608, 1610).

Abstract: A method (40) and apparatus (30) is described for performing image rendering of high resolution computer generated images using limited memory and constrained rendering architectures. An image is segmented into a plurality of tiles (110). A graphics renderer (17), which is usually used for rendering low resolution images onto a display device (19), is used to render one tile (110) at a time. The rendered tile images are combined to form a band of the image (101) and the image data of the band (101) is transferred to a printer engine (20) for printing. Each band (101) is rendered and transferred to the printer engine (20) until the whole image is printed.

Abstract: A method for performing an Inverse Discrete Wavelet Transform is disclosed. The method comprises inverse transforming, using filters (706-710) having specified filter widths, data from associated sub-bands in a first sub-band level, to form processed data in a corresponding sub-band in the second sub-band level. The method further inverse transforms, in a pipeline fashion, using second filters (712-716) having the same corresponding associated filter widths, the processed data in conjunction with corresponding data from associated sub-bands in the second sub-band level.

Abstract: A solid-state ballast for discharge lamps includes circuitry for limiting the maximum output voltage produced when a lamp is first being ignited or is removed. The ballast includes a signal controlled oscillator that provides the operating signal for a resonantly driven lamp load. The voltage across the load is sensed and a signal representing this voltage is fed back to a circuit when controlling the oscillator so as to limit the maximum load voltage during initial start-up and when a lamp is removed. In accordance with a second embodiment, the voltage is cycled between a low level and a level high enough to ignite the lamp, so long as the lamp is not ignited.

Abstract: A solid-state ballast for discharge lamps includes a device for sensing the instantaneous current flowing within the load to produce illumination. A signal representing this load current is differentially processed with an external control signal representing the desired illumination, to produce an removed signal which controls an oscillator that provides the operating signal for the load. In addition, the voltage across the load is sensed and the signal representing this voltage is fed back to a circuit which controls the oscillator so as to limit the maximum load voltage during initial start-up and when a lamp is removed.

Abstract: A circuit is provided to speed up switching of a capacitively coupled power transistor driven with a signal provided from a pulse width modulator. The speed-up circuit is provided across a buffer amplifier which is in series circuit between the pulse width modulator and the coupling capacitor. The speed-up circuit includes a time delay circuit which is activated when the output of the amplifier goes low. The delay circuit is coupled to actuate a clamp circuit at a predetermined interval after activation. The clamp circuit is connected to the input of the amplifier and, upon actuation, pulls up the voltage at the input of the amplifier so that it is at a level intermediate the extreme values of the pulse width modulator output signal. In a preferred embodiment the timer is a series RC charging circuit and the clamp is a transistor with its base connected to the junction between the capacitor and the resistor.