Abstract: The present disclosure is directed to a system and method for continually adapting a channel equalizer that includes a precoder based on changing channel conditions. The precoder is described as being implemented in the exemplary context of a 10GBASE-T physical layer (PHY) device. 10GBASE-T is defined by the Institute of Electrical and Electronics Engineers (IEEE) 802.3an standard and uses four pairs of copper transmission lines to provide an aggregate data rate of 10 gigabits per second. In this exemplary context, the system and method of the present disclosure are configured to exploit an undefined, auxiliary bit in the 10GBASE-T transmission frame to continually send updates to the coefficients of the precoder based on changing channel conditions. The updates can be sent in the transmission frames together with application-level data.

Abstract: The present disclosure is directed to a system and method for continually adapting a channel equalizer that includes a precoder based on changing channel conditions. The precoder is described as being implemented in the exemplary context of a 10GBASE-T physical layer (PHY) device. 10GBASE-T is defined by the Institute of Electrical and Electronics Engineers (IEEE) 802.3an standard and uses four pairs of copper transmission lines to provide an aggregate data rate of 10 gigabits per second. In this exemplary context, the system and method of the present disclosure are configured to exploit an undefined, auxiliary bit in the 10GBASE-T transmission frame to continually send updates to the coefficients of the precoder based on changing channel conditions. The updates can he sent in the transmission frames together with application-level data.

Abstract: Disclosed are various embodiments for reducing the amount of electromagnetic interference (EMI) that may be present in a received signal. A frequency component for the received component is generated. An EMI frequency, an EMI phase, and an EMI amplitude present in the frequency component are tracked. Cancelling data is generated responsive to the EMI frequency, the EMI phase, and the EMI amplitude present in the frequency component.

Abstract: Aspects of a method and system for interference cancellation substantially as shown in and/or described in connection with at least one of the figures, as set forth more completely in the claims. In this regard, a receiver may be operable to receive a differential signal via a differential channel, and to sense a common mode signal on the differential channel. A frequency range in which interference is present in the common mode signal may be determined. The differential signal and the common mode signal may be filtered to attenuate frequencies outside the determined frequency range. A phase and/or amplitude of the filtered common mode signal may be adjusted based on the filtered differential signal and the adjusted and filtered common mode signal may be subtracted from the received differential signal. The common mode signal may be sensed via a pair of resistors coupled to the differential channel.

Abstract: A multi-port transceiver includes a transmitter and receiver for each port. The invention is a test method and apparatus for testing individual components in the transmit and receive paths. Specifically, the invention includes a method of testing the full range of a programmable gain amplifier (PGA) and an analog to digital converter (ADC) in the receive path of each port. This is accomplished by connecting the transmitter of one port directly to the receiver of a second port, and varying the amplitude of the transmitter over a range of gain settings of the PGA while examining if the dynamic range of the receiver has been exceeded.

Abstract: A logic analyzer having internal access to the test buses, clocks and events of a chip is used to debug the chip. The logic analyzer is designed with the capability to share existing memory in the chip during the debug process. Additionally, the configuration of the logic analyzer and observation of the acquired results in the shared memory can be accessed through normal control interfaces of the chip and does not require special test cards. The logic analyzer includes a clocking function, a trigger function, a signal multiplexer, and a memory block. The clocking function is configured to select as the sample clock for the function any of the clocks in the integrated circuit. In addition, the clocking function may provide a means to decimate these clocks by some factor to sample over larger intervals.

Abstract: A data transmitter is provided which performs digital to analog conversion, convolution with an arbitrary finite impulse response, and smoothing of the output functions without requiring a separate anti-aliasing low pass filter. To implement the data transmitter, a digital input data value is convolved with a desired impulse response. The coefficients of the desired finite impulse response filter are chosen to create a first or second derivative of an output of the data transmitter. Then, the derivative is integrated so that a resulting signal output from the data transmitter is a smooth signal which does not require further filtering.

Abstract: Variable length LAN frames can be segmented into fixed length cells to allow the data in the frames to be transported through an intermediate cell-based system, such as an ATM network. Where transport through the intermediate system results in time gaps between data units extracted from the cells, special symbol combinations can be inserted into the time gaps to permit frame-representing data to be forwarded toward its destination as a "stretched frame" without waiting for all the cells representing the frame to arrive. When a stretched LAN frame is received at a "stretch-aware" LAN station, the special symbol combinations are detected and removed to recover at least the data payload of the original LAN frame.