Patents by Inventor John M. Callahan
John M. Callahan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9722605Abstract: An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.Type: GrantFiled: April 25, 2016Date of Patent: August 1, 2017Assignee: Conversant Intellectual Property Management Inc.Inventors: Barry A. Hoberman, Daniel L. Hillman, William G. Walker, John M. Callahan, Michael A. Zampaglione, Andrew Cole
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Publication number: 20160315615Abstract: An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.Type: ApplicationFiled: April 25, 2016Publication date: October 27, 2016Applicant: Conversant Intellectual Property Management Inc.Inventors: Barry A. Hoberman, Daniel L. Hillman, William G. Walker, John M. Callahan, Michael A. Zampaglione, Andrew Cole
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Patent number: 9350349Abstract: An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.Type: GrantFiled: September 8, 2014Date of Patent: May 24, 2016Assignee: Conversant Intellectual Property Management Inc.Inventors: Barry A. Hoberman, Daniel L. Hillman, William G. Walker, John M. Callahan, Michael A. Zampaglione, Andrew Cole
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Publication number: 20140375354Abstract: An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.Type: ApplicationFiled: September 8, 2014Publication date: December 25, 2014Inventors: Barry A. Hoberman, Daniel L. Hillman, William G. Walker, John M. Callahan, Michael A. Zampaglione, Andrew Cole
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Patent number: 8854077Abstract: An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.Type: GrantFiled: August 8, 2012Date of Patent: October 7, 2014Assignee: Conversant Intellectual Property Management Inc.Inventors: Barry A. Hoberman, Daniel L. Hillman, William G. Walker, John M. Callahan, Michael A. Zampaglione, Andrew Cole
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Publication number: 20130027125Abstract: An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.Type: ApplicationFiled: August 8, 2012Publication date: January 31, 2013Inventors: Barry A. Hoberman, Daniel L. Hillman, William G. Walker, John M. Callahan, Michael A. Zampaglione, Andrew Cole
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Patent number: 8253438Abstract: An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.Type: GrantFiled: March 29, 2011Date of Patent: August 28, 2012Assignee: Mosaid Technologies IncorporatedInventors: Barry A. Hoberman, Daniel L. Hillman, William G. Walker, John M. Callahan, Michael A. Zampaglione, Andrew Cole
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Publication number: 20110260785Abstract: An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.Type: ApplicationFiled: March 29, 2011Publication date: October 27, 2011Applicant: MOSAID Technologies IncorporatedInventors: Barry A. Hoberman, Daniel L. Hillman, William G. Walker, John M. Callahan, Michael A. Zampaglione, Andrew Cole
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Patent number: 7940081Abstract: An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.Type: GrantFiled: August 17, 2009Date of Patent: May 10, 2011Assignee: MOSAID Technologies IncorporatedInventors: Barry A. Hoberman, Daniel L. Hillman, William G. Walker, John M. Callahan, Michael A. Zampaglione, Andrew Cole
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Publication number: 20100060319Abstract: An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.Type: ApplicationFiled: August 17, 2009Publication date: March 11, 2010Applicant: MOSAID Technologies CorporationInventors: Barry A. Hoberman, Daniel L. Hillman, William G. Walker, John M. Callahan, Michael A. Zampaglione, Andrew Cole
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Patent number: 7592837Abstract: An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.Type: GrantFiled: September 19, 2008Date of Patent: September 22, 2009Assignee: MOSAID Technologies CorporationInventors: Barry A. Hoberman, Daniel L. Hillman, William G. Walker, John M. Callahan, Michael A. Zampaglione, Andrew Cole
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Publication number: 20090027080Abstract: An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.Type: ApplicationFiled: September 19, 2008Publication date: January 29, 2009Applicant: Mosaid Technologies, Inc.Inventors: Barry A. Hoberman, Daniel L. Hillman, William G. Walker, John M. Callahan, Michael A. Zampaglione, Andrew Cole
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Patent number: 7443197Abstract: An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.Type: GrantFiled: November 30, 2007Date of Patent: October 28, 2008Assignee: Mosaid Technologies, Inc.Inventors: Barry A. Hoberman, Daniel L. Hillman, William G. Walker, John M. Callahan, Michael A. Zampaglione, Andrew Cole
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Patent number: 7348804Abstract: An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.Type: GrantFiled: April 2, 2007Date of Patent: March 25, 2008Assignee: MOSAID Delaware, Inc.Inventors: Barry A. Hoberman, Daniel L. Hillman, William G. Walker, John M. Callahan, Michael A. Zampaglione, Andrew Cole
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Patent number: 7227383Abstract: An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.Type: GrantFiled: January 20, 2005Date of Patent: June 5, 2007Assignee: Mosaid Delaware, Inc.Inventors: Barry A. Hoberman, Daniel L. Hillman, William G. Walker, John M. Callahan, Michael A. Zampaglione, Andrew Cole
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Patent number: 7173851Abstract: A programmable memory cell formed useful in a memory array having column bitlines and row wordlines. The memory cell including a breakdown transistor having its gate connected to a program wordline and a write transistor connected in series at a sense node to said breakdown transistor. The gate of the write transistor is connected to a write wordline. Further, a first sense transistor has its gate connected to the sense node. A second sense transistor is connected in series to the first sense transistor and has its gate connected to a read wordline. The second sense transistor has its source connected to a column bitline.Type: GrantFiled: October 18, 2005Date of Patent: February 6, 2007Assignee: Kilopass Technology, Inc.Inventors: John M. Callahan, Hemanshu T. Vernenker, Michael D. Fliesler, Glen Arnold Rosendale, Harry Shengwen Luan, Zhongshang Liu
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Patent number: 7069482Abstract: To determine the occurrence of an address for a defective memory, cell in a ROM, an error-correction control system includes a comparator that compares a set of incoming memory address signals with static signals provided by a laser-fuse array. The static signals represent addresses of defective memory cells in the ROM. An ADDHIT signal indicates that the ROM has received an address of a defective memory cell. The ADDHIT signal is then timed to provide a REV signal that changes the polarity of the memory bit signal out of a buffer circuit. This corrects an erroneous memory cell by reversing the sense of the memory bit received from a defective memory cell and delivered to an output terminal of the ROM. The REV signal is steered to an output buffer corresponding to the proper ROM chip output pad using a fuse-controlled selection circuit.Type: GrantFiled: August 21, 2000Date of Patent: June 27, 2006Assignee: Nanoamp Solutions, Inc.Inventor: John M. Callahan
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Patent number: 6977860Abstract: A SRAM uses a number of memory banks in a configuration that uses lower voltage swings on a differential internal data bus so that the internal data bus no longer uses single-ended VDD/VSS, HIGH-to-LOW, rail-to-rail voltage swing for a read mode of operation. This consumes less power for a read operation. Senseamps for finally converting low-level signals to full logic output voltage levels are located right next to output buffers and data output pads for the SRAM. The bit lines for a memory CORE are formed in lower metal layers that are closer to the core memory cells and, thus, have higher capacitance. The present invention uses lower-capacitance top layers 4–6 of a 6 metal layer scheme for the signal lines of the differential internal data bus. An optimum configuration has the capacitance of a bitline equal to the capacitance of the differential internal data bus bit-line.Type: GrantFiled: May 22, 2004Date of Patent: December 20, 2005Assignee: Virtual Silicon Technology, Inc.Inventors: Michael J. Tooher, John M. Callahan
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Patent number: 6713855Abstract: A double-sized chip assembly and method is provided for two back-to-back integrated-circuit chips which both have the same fabrication mask sets. An electrically-selectable bonding-pad connection option alternatively provides a standard, non-reversed, option NRO for a bonding-pad layout and a non-standard, reversed option RO for the layout of the bonding-pads. The double-sized, back-to-back, wire-bonded integrated-circuit chip assembly and method includes a pair of integrated-circuit chips, each having one or more reversible wire-bonding-pads. One of the chips has its wire-bonding-pads electrically reversed such that the wire-bonding pads on both chips are located near each other to accommodate wire-bonding to a common bonding finger of a lead frame. A bonding-option wire-bonding-pad has an external voltage applied to it to indicate whether the integrated-circuit chip is to provide a standard pattern for the reversible wire-bonding-pads, or a reversed pattern for the reversible wire-bonding-pads.Type: GrantFiled: December 11, 2001Date of Patent: March 30, 2004Assignee: Nanoamp Solutions, IncInventor: John M. Callahan
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Patent number: 6694448Abstract: A fuse-controlled, row-redundancy control system and method for a SRAM includes a multi-bit, defective-row storage array of static circuits that are programmed to store one of the address bits of a predetermined defective row of the SRAM and that includes a single fuse. The single fuse is blown to indicate a first state of the one of the address bits and is not blown to indicate a second state of the one address bit. The address bits of the predetermined defective row of the SRAM are compared with corresponding address bits of row-address signals received by the SRAM. The comparator includes a fuseless, exclusive logic circuit and provides a RFLAG control signal that indicates that the stored address bits of the defective row of the SRAM match the respective received row address bits for the SRAM.Type: GrantFiled: March 5, 2001Date of Patent: February 17, 2004Assignee: Nanoamp Solutions, Inc.Inventor: John M. Callahan