Abstract: A method for determining fault sources for device failures comprises: generating failure signatures of fault sources for preselected tests; generating aggregate failure signatures for individual of the fault sources from the failure signatures; generating aggregate device test data from test data of a device for the preselected tests; generating aggregate matches by comparing the aggregate failure signatures with the aggregate device test data; and determining fault sources for device failures by comparing the test data of the device with ones of the failure signatures of fault sources corresponding to the aggregate matches. An apparatus configured to perform the method comprises at least one circuit.

Abstract: A tunneling charge injector for use with a MOS floating gate nonvolatile memory cell includes a conducting injector electrode, a grid insulator disposed adjacent the conducting injector electrode, a grid electrode disposed adjacent the grid insulator, a retention insulator which may employ a graded band gap disposed adjacent the grid electrode, and a floating gate disposed adjacent said retention insulator. The floating gate of the tunneling charge injector is coupled to or forms a part of the floating gate of the nonvolatile memory element. Charge is injected from the conducting injector electrode onto the floating gate. Electrons are injected onto the floating gate when the conducting injector electrode is negatively biased with respect to the grid electrode; holes are injected onto the floating gate when the conducting injector electrode is positively biased with respect to the grid electrode.

Abstract: A method for determining fault sources for device failures comprises: generating failure signatures of fault sources for preselected tests; generating aggregate failure signatures for individual of the fault sources from the failure signatures; generating aggregate device test data from test data of a device for the preselected tests; generating aggregate matches by comparing the aggregate failure signatures with the aggregate device test data; and determining fault sources for device failures by comparing the test data of the device with ones of the failure signatures of fault sources corresponding to the aggregate matches. An apparatus configured to perform the method comprises at least one circuit.

Abstract: P channel EEPROM cells are designed for integration into arrays written with single polarity signals developed from small, low power charge pumps. These cells reduce the additional masking steps that must be added to a CMOS logic process for EEPROM to only one additional step. The novel cells of this invention enable the array to function with a VPP about 2 V less than that required by an N channel EEPROM cell, with similar writing speed and tunnel oxide thickness.

Abstract: P channel EEPROM cells are designed for integration into arrays written with single polarity signals developed from small, low power charge pumps. These cells reduce the additional masking steps that must be added to a CMOS logic process for EEPROM to only one additional step. The novel cells of this invention enable the array to function with a VPP about 2 V less than that required by an N channel EEPROM cell, with similar writing speed and tunnel oxide thickness.

Abstract: A tunneling charge injector includes a conducting injector electrode, a grid insulator disposed adjacent the conducting injector electrode, a grid electrode disposed adjacent the grid insulator, a retention insulator disposed adjacent the grid electrode, and a floating gate electrode disposed adjacent the retention insulator. In the tunneling charge injector, charge is injected from the conducting injector electrode onto the floating gate. Electrons are injected onto the floating gate when the conducting injector electrode is negatively biased with respect to the grid electrode, and holes are injected onto the floating gate when the conducting injector electrode is positively biased with respect to the grid electrode. The tunneling charge injector is employed in a nonvolatile memory cell having a nonvolatile memory element with a floating gate such as a floating gate MOS transistor.

Abstract: A tunneling charge injector includes a conducting injector electrode, a grid insulator disposed adjacent the conducting injector electrode, a grid electrode disposed adjacent said grid insulator, a retention insulator disposed adjacent said grid electrode, and a floating gate electrode disposed adjacent said retention insulator. In the tunneling charge injector, charge is injected from the conducting injector electrode onto the floating gate. Electrons are injected onto the floating gate when the conducting injector electrode is negatively biased with respect to the grid electrode, and holes are injected onto the floating gate when the conducting injector electrode is positively biased with respect to the grid electrode. The tunneling charge injector is employed in a nonvolatile memory cell having a nonvolatile memory element with a floating gate such as a floating gate MOS transistor.

Abstract: A tunneling charge injector includes a conducting injector electrode, a grid insulator disposed adjacent the conducting injector electrode, a grid electrode disposed adjacent said grid insulator, a retention insulator disposed adjacent said grid electrode, and a floating gate electrode disposed adjacent said retention insulator. In the tunneling charge injector, charge is injected from the conducting injector electrode onto the floating gate. Electrons are injected onto the floating gate when the conducting injector electrode is negatively biased with respect to the grid electrode, and holes are injected onto the floating gate when the conducting injector electrode is positively biased with respect to the grid electrode. The tunneling charge injector is employed in a nonvolatile memory cell having a nonvolatile memory element with a floating gate such as a floating gate MOS transistor.

Abstract: P channel EEPROM cells are designed for integration into arrays written with single polarity signals developed from small, low power charge pumps. These cells reduce the additional masking steps that must be added to a CMOS logic process for EEPROM to only one additional step. The novel cells of this invention enable the array to function with a VPP about 2 V less than that required by an N channel EEPROM cell, with similar writing speed and tunnel oxide thickness.

Abstract: Apparatus for supplying a signal after a predetermined time delay comprises circuitry for generating a base delay signal that is synchronized to a stable master oscillator insensitive to changes in at least one environmental variable. A vernier signal delay circuit provides delay increments smaller than those available from the base delay signal, the delay increments being sensitive to said at least one environmental variable. Storage circuitry is provided for storing information related to the duration of the delay increments as function of at least one environmental variable for which correction is to be supplied. Sensing circuitry is provided for sensing the at least one environmental variable for which correction is to be provided to supply a sensed at least one environmental variable.

Abstract: P channel EEPROM cells are designed for integration into arrays written with single polarity signals developed from small, low power charge pumps. These cells reduce the additional masking steps that must be added to a CMOS logic process for EEPROM to only one additional step. The novel cells of this invention enable the array to function with a V.sub.PP about 2 V less than that required by an N channel EEPROM cell, with similar writing speed and tunnel oxide thickness.

Abstract: P channel EEPROM cells are designed for integration into arrays written with single polarity signals developed from small, low power charge pumps. These cells reduce the additional masking steps that must be added to a CMOS logic process for EEPROM to only one additional step. The novel cells of this invention enable the array to function with a V.sub.PP about 2 V less than that required by an N channel EEPROM cell, with similar writing speed and tunnel oxide thickness.

Abstract: A programmable interconnect which closely integrates an independent switching transistor with separate NVM programming and erasing elements. The programming element is an EPROM transistor and the erasing element is a Fowler-Nordheim tunneling device. A unitary floating gate is shared by the switching transistor and the NVM programming and elements which charge and discharge the floating gate. The shared floating gate structure is the memory structure of the integrated programmable interconnect and controls the impedance of the switching transistor.

Abstract: An automated system for identification of fabrication defects that lead to the failure of IC products. Design information of the product to be tested is analyzed to identify electrical node-to-node faults that can be caused by fabrication defects. The circuit is then analyzed to determine the electrical response to input patterns which result from the node-to-node faults. A matrix which relates failure responses to a multiplicity of input patterns as a function of process defects is constructed. This response matrix is used to identify the fabrication defect. In those cases in which the response matrix is degenerate, i.e. a set of output responses can arise from more than one fault, knowledge about the probability of occurrence of various defects is used to assign probabilities to the node-to-node faults which may generate the output response set. The system then takes knowledge of a specific IC test system and the response matrix to generate a set of test vectors to analyze a product.

Abstract: An associative memory system and system comprising an M by N array of memory cells forming M words of N trit length are disclosed having single word alterability. Each memory cell further comprises first and second nonvolatile storage devices without the need for additional switching devices. Generally, complementary data is stored in the two storage devices and the cell is interrogated by applying complementary data to the storage devices. A match or mismatch is achieved by looking for current through either of the storage devices. Preferably, the storage devices are one of two types of flash EEPROM transistors, or a SONOS transistor. Each transistor has a gate, drain and source and has write and rewrite capabilities that allows single word alterability in the memory array to be accomplished by applying a high voltage to the transistor drain, or by applying a combination of voltages to the drain and gate.

Abstract: An MOS RAM employing capacitive storage cells where each cell includes a refreshing network which receives an AC signal for refreshing is disclosed. The refreshing signal is applied to the refreshing network through a depletion mode device which acts as a variable capacitor. Lower capacitance is provided when one binary state is stored in the cell, thus preventing undesirable charge from being retained within the cell when the opposite binary state is written into the cell. The refreshing signal is completely asynchronous with memory timing signals; thus, the memory may be accessed at any time.

Abstract: The specification discloses a read only memory constructed from a charge coupled device having a channel for storage of charges in bit regions defined along the channel. Various structures are disclosed for storing combinations of two different levels of charge in the bit regions. In one embodiment, storage gates which communicate at spaced points along the length of the CCD channel are provided with different widths to control the level of charge input by the storage gates to the channel bit regions. In alternate embodiments, the semiconductor doping or oxide thickness of the storage gates are controlled in order to cause different levels of charge to be stored in the channel gate bit regions. After storage of the different charge levels in the channel, phase electrodes which span the channel are operated to serially output the charge levels from the channel to provide a predetermined digital word.