Patents by Inventor John M. Dalbey

John M. Dalbey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Low swing flip-flop with reduced leakage slave latch
    Patent number: 9425775
    Abstract: A data processing system includes first and second power distribution networks to provide power at first and second voltages, and a flip-flop. The second voltage is less than the first voltage. The flip-flop includes a master latch with a power node connected to the first power distribution network, a data signal input, and an output signal output that is driven at the first voltage, and a slave latch with a power node connected to the first power distribution network, an input coupled to the output of the master latch, a slave latch output signal output that is driven by the first voltage, and a feedback circuit with a first latch inverter having a power node connected to the second voltage, an input coupled to the master latch output, and an output terminal to provide an output signal that is driven by the second voltage.
    Type: Grant
    Filed: September 9, 2014
    Date of Patent: August 23, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Anis M. Jarrar, John M. Dalbey, Alexander B. Hoefler, Colin MacDonald
  • LOW SWING FLIP-FLOP WITH REDUCED LEAKAGE SLAVE LATCH
    Publication number: 20160072484
    Abstract: A data processing system includes first and second power distribution networks to provide power at first and second voltages, and a flip-flop. The second voltage is less than the first voltage. The flip-flop includes a master latch with a power node connected to the first power distribution network, a data signal input, and an output signal output that is driven at the first voltage, and a slave latch with a power node connected to the first power distribution network, an input coupled to the output of the master latch, a slave latch output signal output that is driven by the first voltage, and a feedback circuit with a first latch inverter having a power node connected to the second voltage, an input coupled to the master latch output, and an output terminal to provide an output signal that is driven by the second voltage.
    Type: Application
    Filed: September 9, 2014
    Publication date: March 10, 2016
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Anis M. Jarrar, John M. Dalbey, Alexander B. Hoefler, Colin MacDonald
  • System and method for reducing the power consumption of clock systems
    Patent number: 7418675
    Abstract: A system an method of designing an integrated circuit identifies a plurality of synchronous cells of an integrated circuit to be driven by a clock driver, wherein the plurality of synchronous cells are a subset of previously placed cells of the integrated circuit. The placement of synchronous cells is performed to reduce a current needed from the clock driver to drive the plurality of synchronous cells.
    Type: Grant
    Filed: January 30, 2006
    Date of Patent: August 26, 2008
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Colin MacDonald, John M. Dalbey, Anis M. Jarrar