Patents by Inventor John M DeLucca

John M DeLucca has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10014439
    Abstract: Aspects of the disclosure pertain to a system and method for providing an electron blocking layer with doping control. The electron blocking layer is included in a semiconductor assembly. The electron blocking layer includes a lithium aluminate layer. The lithium aluminate layer promotes reduced diffusion of magnesium into a layer stack of the semiconductor assembly.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: July 3, 2018
    Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventors: Joseph M. Freund, John M. DeLucca
  • Publication number: 20160329463
    Abstract: Aspects of the disclosure pertain to a system and method for providing an electron blocking layer with doping control. The electron blocking layer is included in a semiconductor assembly. The electron blocking layer includes a lithium aluminate layer. The lithium aluminate layer promotes reduced diffusion of magnesium into a layer stack of the semiconductor assembly.
    Type: Application
    Filed: July 21, 2016
    Publication date: November 10, 2016
    Inventors: Joseph M. Freund, John M. DeLucca
  • Patent number: 9425050
    Abstract: Aspects of the disclosure pertain to a system and method for providing an electron blocking layer with doping control. The electron blocking layer is included in a semiconductor assembly. The electron blocking layer includes a lithium aluminate layer. The lithium aluminate layer promotes reduced diffusion of magnesium into a layer stack of the semiconductor assembly.
    Type: Grant
    Filed: August 19, 2013
    Date of Patent: August 23, 2016
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Joseph M. Freund, John M. DeLucca
  • Patent number: 9136245
    Abstract: An electronic device comprising a bond pad on a substrate and a wire bonded to the bond pad. The device further comprises an intermetallic compound interface located between the bond pad and the wire and a silicon nitride or silicon carbonyl layer covering the intermetallic compound interface.
    Type: Grant
    Filed: May 21, 2014
    Date of Patent: September 15, 2015
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd
    Inventors: John M. DeLucca, Ronald J. Weachock, Barry J. Dutt, Frank A. Baiocchi, John W. Osenbach
  • Publication number: 20150048310
    Abstract: Aspects of the disclosure pertain to a system and method for providing an electron blocking layer with doping control. The electron blocking layer is included in a semiconductor assembly. The electron blocking layer includes a lithium aluminate layer. The lithium aluminate layer promotes reduced diffusion of magnesium into a layer stack of the semiconductor assembly.
    Type: Application
    Filed: August 19, 2013
    Publication date: February 19, 2015
    Applicant: LSI Corporation
    Inventors: Joseph M. Freund, John M. DeLucca
  • Publication number: 20140349475
    Abstract: An electronic device comprising a bond pad on a substrate and a wire bonded to the bond pad.
    Type: Application
    Filed: May 21, 2014
    Publication date: November 27, 2014
    Applicant: LSI Corporation
    Inventors: John M. DeLucca, Ronald J. Weachock, Barry J. Dutt, Frank A. Baiocchi, John W. Osenbach
  • Patent number: 8766436
    Abstract: An electronic device comprising a bond pad on a substrate and a wire bonded to the bond pad. The device further comprises an intermetallic compound interface located between the bond pad and the wire and a silicon nitride or silicon carbonyl layer covering the intermetallic compound interface.
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: July 1, 2014
    Assignee: LSI Corporation
    Inventors: John M. DeLucca, Frank A. Baiocchi, Ronald J. Weachock, John W. Osenbach, Barry J. Dutt
  • Patent number: 8744529
    Abstract: An apparatus comprises a first housing having a top surface and a bottom surface, a second housing having a top surface and a bottom surface, and one or more supports coupling the first housing to the second housing such that the first and second housings are electrically connected and the bottom surface of the first housing overlays the top surface of the second housing. The one or more supports are configurable in at least a first configuration wherein the bottom surface of the first housing and the top surface of the second housing are substantially contiguous with one another and a second configuration wherein the bottom surface of the first housing and the top surface of the second housing are separated by a space.
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: June 3, 2014
    Assignee: LSI Corporation
    Inventors: Joseph M. Freund, Roger A. Fratti, John M. DeLucca
  • Publication number: 20140057682
    Abstract: An apparatus comprises a first housing having a top surface and a bottom surface, a second housing having a top surface and a bottom surface, and one or more supports coupling the first housing to the second housing such that the first and second housings are electrically connected and the bottom surface of the first housing overlays the top surface of the second housing. The one or more supports are configurable in at least a first configuration wherein the bottom surface of the first housing and the top surface of the second housing are substantially contiguous with one another and a second configuration wherein the bottom surface of the first housing and the top surface of the second housing are separated by a space.
    Type: Application
    Filed: August 27, 2012
    Publication date: February 27, 2014
    Applicant: LSI Corporation
    Inventors: Joseph M. Freund, Roger A. Fratti, John M. DeLucca
  • Patent number: 8610215
    Abstract: An electronic device includes a semiconductor substrate and a dielectric layer over the substrate. A resistive link located over the substrate includes a first resistive region and a second resistive region. The first resistive region has a first resistivity and a first morphology. The second resistive region has a second resistivity and a different second morphology.
    Type: Grant
    Filed: September 19, 2008
    Date of Patent: December 17, 2013
    Assignee: Agere Systems LLC
    Inventors: Frank A. Baiocchi, James T. Cargo, John M. DeLucca, Barry J. Dutt, Charles Martin
  • Publication number: 20130094838
    Abstract: A method for managing playback of special feature content on an optical disc, comprising the steps of (A) storing a first disc specific information set for a particular disc in the memory of an optical disc player and (B) prior to playback of a main feature content, comparing a previously stored second disc specific information to the first disc specific information of a current disc and (C) if a match occurs between the first disc specific information and the second disc specific information, skipping the loading or playback of the special feature content on the optical disc and playing said main feature content.
    Type: Application
    Filed: October 17, 2011
    Publication date: April 18, 2013
    Inventors: Joseph M. Freund, John M. DeLucca
  • Publication number: 20120223432
    Abstract: An electronic device comprising a bond pad on a substrate and a wire bonded to the bond pad.
    Type: Application
    Filed: March 1, 2011
    Publication date: September 6, 2012
    Applicant: LSI Corporation
    Inventors: JOHN M. DELUCCA, FRANK A. BAIOCCHI, RONALD J. WEACHOCK, JOHN W. OSENBACH, BARRY J. DUTT
  • Publication number: 20120204941
    Abstract: A method provides forming a photovoltaic (PV) cell. The PV cell may be, e.g. a heterojunction with intrinsic thin layer (HIT) cell. The method includes forming a crystalline semiconductor layer over a substrate. The crystalline semiconductor layer is heated above a melting temperature of the semiconductor. A portion of the crystalline semiconductor layer is thereby converted to a quenched amorphous semiconductor layer.
    Type: Application
    Filed: February 15, 2011
    Publication date: August 16, 2012
    Inventors: James T. Cargo, Frank A. Baiocchi, John M. DeLucca
  • Publication number: 20120111927
    Abstract: A method of forming an electronic device bond pad includes providing an electronic device substrate having an Al bond pad located thereover. An aluminum layer is formed over the Al bond pad. A metal layer is formed located between the Al bond pad and the aluminum layer. The metal layer comprises one or more of Ni, Pd and Pt and has a total concentration of Ni, Pd and/or Pt of at least about 50 wt. %. A gold bond wire may be attached to the aluminum layer.
    Type: Application
    Filed: January 5, 2012
    Publication date: May 10, 2012
    Applicant: LSI Corporation
    Inventors: Frank A. Baiocchi, John M. DeLucca, John W. Osenbach
  • Publication number: 20120033479
    Abstract: An electronic device includes a substrate with a resistive element located thereover. The resistive element includes a semiconductor region. A read module is configured to determine a resistance of the resistive element. A programming module is configured to cause a current to flow through the semiconductor region. The current is sufficient to induce a change of morphology of at least a portion of the semiconductor region.
    Type: Application
    Filed: August 6, 2010
    Publication date: February 9, 2012
    Applicant: LSI Corporation
    Inventors: John M. DeLucca, James Cargo, Frank A. Baiocchi
  • Patent number: 8101871
    Abstract: An electronic device bond pad includes an Al layer located over an electronic device substrate. The Al layer includes an intrinsic group 10 metal located therein.
    Type: Grant
    Filed: May 26, 2009
    Date of Patent: January 24, 2012
    Assignee: LSI Corporation
    Inventors: Frank A. Baiocchi, John M DeLucca, John W. Osenbach
  • Publication number: 20110163419
    Abstract: An electronic device includes a semiconductor substrate and a dielectric layer over the substrate. A resistive link located over the substrate includes a first resistive region and a second resistive region. The first resistive region has a first resistivity and a first morphology. The second resistive region has a second resistivity and a different second morphology.
    Type: Application
    Filed: September 19, 2008
    Publication date: July 7, 2011
    Applicant: AGERE SYSTEMS INC.
    Inventors: Frank A. Baiocchi, James T. Cargo, John M. DeLucca, Barry J. Dutt, Charles Martin
  • Publication number: 20100300741
    Abstract: An electronic device bond pad includes an Al layer located over an electronic device substrate. The Al layer includes an intrinsic group 10 metal located therein.
    Type: Application
    Filed: May 26, 2009
    Publication date: December 2, 2010
    Applicant: LSI Corporation
    Inventors: Frank A. Baiocchi, John M. DeLucca, John W. Osenbach