Abstract: Embodiments of the inventive concept include a computer-implemented method for intelligently swapping circuit cells and an associated intelligent cell swapper logic section. The technique can include receiving, by an intelligent cell swapper logic section, a synthesized gate level netlist including cells each having an initial cell class. A cell class sorter can sort cell classes in order of leakage. A ceiling finder can swap the initial cell class for each of the cells to a highest cell leakage class, and determine a ceiling frequency. A floor finder can swap the highest cell leakage class for each of the cells to a lowest cell leakage class, and determine a floor frequency. An effective swap weight calculator section can determine an effective swap weight for a subset of cells based on cell attribute weighting criteria. The timing paths can be optimized to meet the ceiling frequency without unnecessarily using high leakage cells.

Abstract: According to one aspect, a method may include receiving a circuit model that includes a clock mesh that controls each of a plurality of logic circuits by inputting a respective clock signal to an end-point of each logic circuit. The method may include providing an incremental latency adjustment to the circuit model by determining one or more end-points that are candidates for adjustment of a respective end-point's clock skew schedule. And, for each end-point that is associated with a negative front slack, adjusting a clock skew schedule of an end-point by a quantized amount. Further, for each end-point that is associated with a negative back-slack, adjusting the clock skew schedule of an end-point that is associated by a quantized amount. The method may also include repeating, the step of providing an incremental timing update. The method may include performing a timing evaluation upon the circuit model.

Abstract: Embodiments of the inventive concept include a computer-implemented method for intelligently swapping circuit cells and an associated intelligent cell swapper logic section. The technique can include receiving, by an intelligent cell swapper logic section, a synthesized gate level netlist including cells each having an initial cell class. A cell class sorter can sort cell classes in order of leakage. A ceiling finder can swap the initial cell class for each of the cells to a highest cell leakage class, and determine a ceiling frequency. A floor finder can swap the highest cell leakage class for each of the cells to a lowest cell leakage class, and determine a floor frequency. An effective swap weight calculator section can determine an effective swap weight for a subset of cells based on cell attribute weighting criteria. The timing paths can be optimized to meet the ceiling frequency without unnecessarily using high leakage cells.

Abstract: According to one aspect, a method may include receiving a circuit model that includes a clock mesh that controls each of a plurality of logic circuits by inputting a respective clock signal to an end-point of each logic circuit. The method may include providing an incremental latency adjustment to the circuit model by determining one or more end-points that are candidates for adjustment of a respective end-point's clock skew schedule. And, for each end-point that is associated with a negative front slack, adjusting a clock skew schedule of an end-point by a quantized amount. Further, for each end-point that is associated with a negative back-slack, adjusting the clock skew schedule of an end-point that is associated by a quantized amount. The method may also include repeating, the step of providing an incremental timing update. The method may include performing a timing evaluation upon the circuit model.