Abstract: A method and apparatus for filtering failures due to must-repair rows or columns from a memory test fail summary image includes current available redundant row failure counts respectively associated with rows of a memory device and current available redundant column failure counts associated with columns of the device. Respective failure counts are preloaded with the respective values of redundant rows and columns available for repairing the device. When failures in memory cells of the device are encountered, either during test, or during scan of an earlier generated error image, the row and column failure counts associated with the rows and columns containing the memory cell failures are decremented. At the end of a test, the value of the failure counts indicates whether the corresponding row or column contain any failures at all, whether the corresponding row or column is designated as a “must-repair” row or column, and otherwise how many errors the corresponding row or column contain.

Abstract: A method and apparatus permits use of a tester memory (31) as storage for an inversion mask. The inversion mask indicates to the tester which cells in a DUT memory (14) are logically inverted during testing. Data information and the inverse of the data information is input into a first data multiplexer (802). The stored inversion mask (902–908) is used to independently select a data information bit or its inverse for presentation as a masked output (814) at the output of the first data multiplexer (802).

Abstract: A trigger signal for a memory tester uses a (breakpoint) trigger qualified according to what part of the test program is being executed. The qualified breakpoint trigger can be delayed before becoming a system trigger signal that can be used to trigger a ‘scope mode and to force an error flag to a selected value so as to compel a particular path with the test program. To provide stable waveforms for the sweeping of the voltage thresholds and sample timing offset the memory tester records the addresses for a target sequence of transmit vectors issued during an initial pass through the test program subsequent to the occurrence of the trigger. These addresses are exchanged for the instructions themselves, which are then altered to remove branching, and stored in a reserved portion of the memory they came from. Once the altered target sequence is stored the desired information is produced by restarting the entire test program and letting it run exactly as before down to the trigger.

Abstract: A method and apparatus for coordinating program execution in a site controller with pattern execution in a tester executes the pattern in the tester and a pattern interruption instruction. The pattern interruption instruction causes the tester to write to a service request register in the site controller specifying a value that specifies a requested subroutine and a data source. The site controller initiates execution of the requested subroutine in the site controller using the specified data source.

Abstract: A test program generates transmit vectors (stimuli) and receive vectors (expected responses). The transmit vectors are applied to the DUT, while the receive vectors are treated as comparison values used to decide if a response from the DUT is as expected. While programming a FLASH part the test program uses TAG RAM techniques to maintain a BAD COLUMN table in one of the memory sets. This BAD COLUMN table is addressed by the same address that is applied to the DUT. If an OMIT BAD COLUMN mode is in effect, entries in this table are, by automatic action of the memory tester hardware, obtained and used to supply a replacement programming data value of all 1's that will produce an immediate and automatic indication of successful programming from the DUT. This prevents spending extra time programming a column that has been determined to be bad, without requiring an alteration in the internal mechanism of the test program.

Abstract: The data path into a post decode mechanism is altered to allow post decode to process data before or as that data is placed into a destination memory structure in interior test memory. Other data will continue to be first placed into a memory structure in interior test memory before being applied to the post decode mechanism. Extensive masking capability coupled with copies of error tables allow incremental post decode analysis for a new test, and avoids counting of errors in locations that are already known to have failed during previous tests. Both errors within words and bit errors can be accumulated. The post decode mechanism is often capable of producing multiple type of results from a single pass through the data, whether applied on the fly or from a structure in interior test memory. The post decode mechanism has counters that count down from pre-loaded values representing thresholds for deciding something about error activity. A counts of zero produces a terminal count flag.

Abstract: An apparatus for automatically accumulating and storing information has a destination memory and an indexing circuit. The indexing circuit has an input port, a selector having a selector output, a register holding a value from the selector output and presenting the selector output value at a register output, and an accumulator accepting a value from the input port and a value from the register output and presenting a sum of the input port and register output values at an accumulator output. The selector receives the input port value from the input port, the accumulator output, and the value from the register output, the selector output being based upon a programmable selection code. The register output is connected to the destination memory .

Abstract: A memory tester supports testing of multiple DUT's of the same type at a test site. The tester can be instructed to replicate the segments of the test vectors needed to test one DUT on the channels for the other DUT's. This produces patterns of transmit and receive vectors that are n-many DUT's wide. Conditional branching within the test program in response to conditions in the receive vectors (DUT failure) is supported by recognizing several types of error indications and an ability to selectively disable the testing of one or more DUT's while continuing to test the one or more that are not disabled. Also included are ways to remove or limit stimulus to particular DUT's, and ways to make all comparisons for a particular DUT appear to be “good.

Abstract: A memory tester has a feature including a method and an apparatus, to programmably insert a latency between address and data channels. Address information is stored in a FIFO memory during a first program instruction cycle. After a desired number of program instruction cycles, the address information is retrieved during a second program instruction cycle. The retrieved address information is used to address a location in a tester memory for storage of data information received from a DUT. In this way, the data information is correlated to a latent address according to DUT specifications.

Abstract: A trigger signal for a memory tester having algorithmic test programs detects the occurrence of a trigger specification expressed in terms of existing hardware quantities used to operate the DUT. This forms a raw hardware (breakpoint) trigger that can be further qualified according to what part of the test program is being executed. The qualified breakpoint trigger can be delayed by zero or more DUT cycles before becoming a system trigger signal that can be used to trigger a ‘scope mode and to force an error flag to a selected value so as to compel a particular path with the test program. A user interacts with a process not part of the test program to define a trigger specification from masks and comparison mechanisms that recognize the raw trigger condition at the level of the hardware register values. That process also informs the compiler as to which portions of the test program are to enable the raw trigger specification (done by setting a bit in the instruction word).