Abstract: Two techniques are provided for implementing a least recently used (LRU) replacement algorithm for multi-way associative caches. A first method uses a special encoding of the LRU list to allow write only update of the list. The LRU list need only be read when a miss occurs and a replacement is needed. In a second method, the LRU list is integrated into the tags for each "way" of the multi-way associative cache. Updating of the list is done by writing only the "way" of the cache that hits.

Abstract: A vector processing computer is configured to operate in a pipelined fashion wherein each of the functional units is essentially independent and is designed to carry out its operational function in the fastest possible manner. Vector elements are transmitted from memory, either main memory, a physical cache unit or a logical cache through a source bus where the elements are alternately loaded into the vector processing units. The vector control unit decodes the vector instructions and generates the required control commands for operating the registers and logical units within the vector processing units. Thus, the vector processing units essentially work in parallel to double the processing rate. The resulting vectors are transmitted through a destination bus to either the physical cache unit, the main memory, the logical cache or to an input/output processor.