Patents by Inventor John M. Golio
John M. Golio has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 5631175Abstract: A field effect transistor (10) has an active layer (16) formed in a substrate (12). A gate (20) is disposed on an elevated platform (18) formed from the active layer (16). The elevated platform (18) raises the bottom surface (21) of the gate (20) relative to the top surface (34, 36) of the active region (13) on either side of the gate (20). A fabrication method for the transistor (10) forms the elevated platform (18) by etching the active region surface (44) on both sides of the gate (20) so that the bottom surface (21) of the gate (20) is elevated relative to the top surface (34) of the surrounding active region (13). The gate (20) itself and/or a patterned photoresist layer (116) may be used as a mask for performing this etch.Type: GrantFiled: January 17, 1996Date of Patent: May 20, 1997Assignee: Motorola, Inc.Inventors: James G. Gilbert, Lawrence S. Klingbeil, Jr., David J. Halchin, John M. Golio
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Patent number: 5615473Abstract: A semiconductor substrate with electronic circuitry (e.g., a transmitter or receiver) formed thereon and including interconnects. A ferrite disk bonded to the substrate so as to interact with the interconnects, when the ferrite disk is activated by a substantially constant magnetic field thereacross, to provide frequency selectivity within the electronic circuitry. A permanent magnet positioned adjacent to the ferrite disk to provide a substantially constant magnetic field across the ferrite disk so that the magnetic field produces resonance in the ferrite disk.Type: GrantFiled: May 30, 1995Date of Patent: April 1, 1997Assignee: MotorolaInventors: Michael Dydyk, John M. Golio, Robert J. Higgins, Jr., Aristotelis Arvanitis
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Patent number: 5590063Abstract: A method executed by a computer for performing numerical optimization of arbitrary functions in a computer model using parallel processors (10, 12, 14). The method initializes (20) each processor with an initial estimate of the parameter value to be optimized. The initial estimate is evaluated (22) in each processor to determine a solution. A best estimate of the parameter value from the result in each processor is selected (24), and one or more of the parallel processors with the best estimate is set to run in gradient mode while the remaining processors run in random mode (26). The estimates of the parameter value from the processors running in random mode is evaluated until a local minimum is obtained from the processor running in gradient mode (28). The process is repeated until an optimal solution is found (34).Type: GrantFiled: July 5, 1994Date of Patent: December 31, 1996Assignee: Motorola, Inc.Inventors: John M. Golio, Robert C. Turner, Monte G. Miller, David J. Halchin
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Patent number: 5508539Abstract: A field effect transistor (10) has an active layer (16) formed in a substrate (12). A gate (20) is disposed on an elevated platform (18) formed from the active layer (16). The elevated platform (18) raises the bottom surface (21) of the gate (20) relative to the top surface (34, 36) of the active region (13) on either side of the gate (20). A fabrication method for the transistor (10) forms the elevated platform (18) by etching the active region surface (44) on both sides of the gate (20) so that the bottom surface (21) of the gate (20) is elevated relative to the top surface (34) of the surrounding active region (13). The gate (20) itself and/or a patterned photoresist layer (116) may be used as a mask for performing this etch.Type: GrantFiled: April 20, 1995Date of Patent: April 16, 1996Assignee: Motorola, Inc.Inventors: James G. Gilbert, Lawrence S. Klingbeil, Jr., David J. Halchin, John M. Golio
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Patent number: 5477137Abstract: A method and apparatus for a probeable substrate substitute for a calibration standard and test fixture. The probestrate includes a dielectric substrate having first and second dielectric substrate surfaces and at least one conductive via hole through the dielectric substrate from the first dielectric substrate surface to the second dielectric substrate surface. A first metalized layer is in contact with the first dielectric substrate surface and the at least one conductive via hole. A second metalized layer is in contact with a first portion of the second dielectric substrate surface and with the at least one conductive via hole. The first and second test ports contact a second portion of the second dielectric substrate surface. An electronic device can be connected to the first and second test ports with bond wires for characterization via contact of the first and second test ports with standard test station equipment.Type: GrantFiled: October 2, 1992Date of Patent: December 19, 1995Assignee: Motorola, Inc.Inventors: Joseph Staudinger, John M. Golio, Warren L. Seely
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Patent number: 5424698Abstract: A semiconductor substrate with electronic circuitry (e.g., a transmitter or receiver) formed thereon and including interconnects. A ferrite disk bonded to the substrate so as to interact with the interconnects, when the ferrite disk is activated by a substantially constant magnetic field thereacross, to provide frequency selectivity within the electronic circuitry. A permanent magnet positioned adjacent to the ferrite disk to provide a substantially constant magnetic field across the ferrite disk so that the magnetic field produces resonance in the ferrite disk.Type: GrantFiled: December 6, 1993Date of Patent: June 13, 1995Assignee: Motorola, Inc.Inventors: Michael Dydyk, John M. Golio, Robert J. Higgins, Jr., Aristotelis Arvanitis
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Patent number: 5410743Abstract: A mixer separates IF components IF1, IF2 of the same frequency which are images of different frequency RF signals RF1, RF2 beating with a given LO signal. The LO signal is applied to a FET active power divider and applied to the drains of a pair of balanced FET mixing elements. The FETs for the active power divider are built from the same device structure as the FETs for the mixing elements sharing drain nodes. The RF signals are passed through a quadrature phase shifter and applied to the gates of the FET mixing elements. The mixed signals appear at the drains of FET mixing elements are applied to opposing ports of a second quadrature hybrid at whose output ports the separated IF output signals IF1, IF2 appear.Type: GrantFiled: June 14, 1993Date of Patent: April 25, 1995Assignee: Motorola, Inc.Inventors: Warren L. Seely, Joseph Staudinger, John M. Golio
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Patent number: 5345123Abstract: An attenuator circuit uses single point control to adjust the attenuation levels between first and second nodes. The attenuator is set-up as a .pi.-network with a pass transistor and first and second shunt transistors. Capacitors are coupled in the drain and source conduction paths of the first and second shunt transistors for DC isolation to float the shunt transistors. A control voltage applied at the drain of the pass transistor and the gates of the first and second shunt transistors controls the attenuation level. A parallel resistor and capacitor combination at the drain of the first shunt transistor provides tuning to match the input impedance of the attenuator to the sourcing circuit.Type: GrantFiled: July 7, 1993Date of Patent: September 6, 1994Assignee: Motorola, Inc.Inventors: Joseph Staudinger, John M. Golio, William B. Beckwith, Jean B. Verdier
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Patent number: 5265269Abstract: An apparatus for mixing electrical signals including in combination: first signal splitting means having a radio frequency (RF) port and first, second, third and fourth signal ports, second signal splitting means having a local oscillator (LO) port and first, second, third and fourth signal ports, intermediate frequency (IF) port, and mixer element means, the mixer element means coupled to the first, second, third, and fourth signal ports of the first and second signal splitting means and coupled to the intermediate frequency port means, for mixing two of the RF, IF, and LO signals to produce the remaining signal.Type: GrantFiled: June 21, 1991Date of Patent: November 23, 1993Assignee: Motorola, Inc.Inventors: Joseph Staudinger, Warren L. Seely, John M. Golio
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Patent number: 5220194Abstract: A variable field effect capacitive device suitable for providing different amounts of capacitance in response to control signals of different magnitudes. The device includes a pair of plate electrodes and a pair of control electrodes. A semiconductor region is located between the control electrodes. The plates each make Schottky contact to the semiconductor region to form a depletion region therein which changes shape in response to changes in the magnitude of the control signals.Type: GrantFiled: May 4, 1991Date of Patent: June 15, 1993Assignee: Motorola, Inc.Inventors: John M. Golio, Ronald J. Massey, Monte G. Miller
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Patent number: 5043993Abstract: Optical signal frequency conversion and mixing is accomplished by an optical device comprised of a photodetector, a non-linear device, passive circuitry, and a multiple quantum well structure. The photodetector converts a light signal into an electrical signal. The non-linear devices create harmonics of the electrical signal of which the passive circuitry selects a desired frequency of the harmonics. This selected frequency in turn modulates the multiple quantum well structure. A power bias is applied to the multiple quantum well structure which is then modulated by it to produce a modulated output light beam modulated at the selected frequency.Type: GrantFiled: April 30, 1990Date of Patent: August 27, 1991Assignee: Motorola, Inc.Inventors: John M. Golio, Earnest J. Johnson
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Patent number: 5005059Abstract: A field effect device and circuit suitable for providing an analog output signal having a magnitude which is representative of a digital input code having a sequence of bits. The device includes a plurality of gate electrodes located between an input electrode and an output electrode. The gate electrodes have unequal lengths to provide different gate widths each representative of the magnitude of a portion of an analog signal provided at the output electrode in response to a digital signal of a particular logic state, such as a logical "one", when applied to any one of the gate electrodes. Thus, the magnitude of the current conducted between the input electrode and the output electrode is responsive to the sum of the widths of the gates receiving the digital signal of a particular logic state.Type: GrantFiled: May 1, 1989Date of Patent: April 2, 1991Assignee: Motorola, Inc.Inventors: John M. Golio, Joseph Staudinger
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Patent number: 5001524Abstract: A variable field effect attenuator suitable for providing digitally controlled attenuation characteristic is disclosed. The attenuator can include a first semiconductor region connected in a series path between the input and output terminals and at least one shunt semiconductor region connected between the series path and a reference potential conductor. First gate electrodes are arranged to operate with the series semiconductor region and second gate electrodes are arranged to operate with the shunt semiconductor region. Gate electrode control lines are connected to selected gate electrodes so that digital signals can be selectively applied to the gate electrodes to render the semiconductor material associated therewith either conductive or nonconductive to provide a plurality of predetermined amounts of attenuation between the input and output terminals in response to a digital code.Type: GrantFiled: June 5, 1989Date of Patent: March 19, 1991Assignee: Motorola, Inc.Inventors: John M. Golio, Janet R. J. Golio, Joseph Staudinger
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Patent number: 4998147Abstract: Overlapping gate electrodes are selectively energized to vary the electrical length and thus the resistance of the conductive path through a field effect attenuator. The electrical width can also be varied to provide additional control over the resistance.Type: GrantFiled: July 31, 1989Date of Patent: March 5, 1991Assignee: Motorola, Inc.Inventors: William B. Beckwith, John M. Golio
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Patent number: 4849716Abstract: An optical injection locking oscillator is comtemplated having a tuning device. The tuning device generates a DC voltage proportional to the resonant frequency of a modulated light used to injection lock the free running oscillator. The DC voltage is applied to a varactor capacitor within the oscillator to bring the frequency of oscillation within a close proximity to the modulating frequency of the light. This facilitates injection locking, whereas frequencies of oscillation outside a certain locking range will not facilitate injection locking. The modulated light then locks the oscillator into a desired resonant frequency. A second embodiment contemplates using a YIG oscillator regulated by a DC current generated within the tuning device.Type: GrantFiled: August 15, 1988Date of Patent: July 18, 1989Assignee: Motorola, Inc.Inventors: John M. Golio, David A. Warren