Patents by Inventor John M. Hergenrother
John M. Hergenrother has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7943486Abstract: The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a Si-containing layer having a <110> crystal orientation and a biaxial compressive strain. The term “biaxial compressive stress” is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing <110> layer; and creating a biaxial strain in the silicon-containing <110> layer.Type: GrantFiled: May 6, 2008Date of Patent: May 17, 2011Assignee: International Business Machines CorporationInventors: Victor Chan, Massimo V. Fischetti, John M. Hergenrother, Meikei Ieong, Rajesh Rengarajan, Alexander Reznicek, Paul M. Solomon, Chun-yung Sung, Min Yang
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Patent number: 7859061Abstract: Superior control of short-channel effects for an ultra-thin semiconductor-on-insulator field effect transistor (UTSOI-FET) is obtained by performing a halo implantation immediately after a gate reoxidation step. An offset is then formed and thereafter an extension implantation process is performed. This sequence of processing steps ensures that the halo implant is laterally separated from the extension implant by the width of the offset spacer. This construction produces equivalent or far superior short channel performance compared to conventional UTSOI-FETs. Additionally, the above processing steps permit the use of lower halo doses as compared to conventional processes.Type: GrantFiled: August 8, 2009Date of Patent: December 28, 2010Assignee: International Business Machines CorporationInventors: Omer H. Dokumaci, John M. Hergenrother, Shreesh Narasimha, Jeffrey W. Sleight
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Publication number: 20090305471Abstract: The present invention provides a semiconducting device structure including a thin SOI region, wherein the SOI device is formed with an optional single thin diffusion, i.e., offset, spacer and a single diffusion implant. The device silicon thickness is thin enough to permit the diffusion implants to abut the buried insulator but thick enough to form a contacting silicide. Stress layer liner films are used both over nFET and pFET device regions to enhance performance.Type: ApplicationFiled: August 14, 2009Publication date: December 10, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Leland Chang, David M. Fried, John M. Hergenrother, Ghavam Shahidi, Jeffrey W. Sleight
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Publication number: 20090294854Abstract: Superior control of short-channel effects for an ultra-thin semiconductor-on-insulator field effect transistor (UTSOI-FET) is obtained by performing a halo implantation immediately after a gate reoxidation step. An offset is then formed and thereafter an extension implantation process is performed. This sequence of processing steps ensures that the halo implant is laterally separated from the extension implant by the width of the offset spacer. This construction produces equivalent or far superior short channel performance compared to conventional UTSOI-FETs. Additionally, the above processing steps permit the use of lower halo doses as compared to conventional processes.Type: ApplicationFiled: August 8, 2009Publication date: December 3, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Omer H. Dokumaci, John M. Hergenrother, Shreesh Narasimha, Jeffrey W. Sleight
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Patent number: 7595247Abstract: Superior control of short-channel effects for an ultra-thin semiconductor-on-insulator field effect transistor (UTSOI-FET) is obtained by performing a halo implantation immediately after a gate reoxidation step. An offset is then formed and thereafter an extension implantation process is performed. This sequence of processing steps ensures that the halo implant is laterally separated from the extension implant by the width of the offset spacer. This construction produces equivalent or far superior short channel performance compared to conventional UTSOI-FETs. Additionally, the above processing steps permit the use of lower halo doses as compared to conventional processes.Type: GrantFiled: May 25, 2007Date of Patent: September 29, 2009Assignee: International Business Machines CorporationInventors: Omer H. Dokumaci, John M. Hergenrother, Shreesh Narasimha, Jeffrey W. Sleight
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Patent number: 7462525Abstract: The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a Si-containing layer having a <110> crystal orientation and a biaxial compressive strain. The term “biaxial compressive stress” is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing <110> layer; and creating a biaxial strain in the silicon-containing <110> layer.Type: GrantFiled: October 25, 2007Date of Patent: December 9, 2008Assignee: International Business Machines CorporationInventors: Victor Chan, Massimo V. Fischetti, John M. Hergenrother, Meikei Ieong, Rajesh Rengarajan, Alexander Reznicek, Paul M. Solomon, Chun-yung Sung, Min Yang
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Publication number: 20080290409Abstract: Superior control of short-channel effects for an ultra-thin semiconductor-on-insulator field effect transistor (UTSOI-FET) is obtained by performing a halo implantation immediately after a gate reoxidation step. An offset is then formed and thereafter an extension implantation process is performed. This sequence of processing steps ensures that the halo implant is laterally separated from the extension implant by the width of the offset spacer. This construction produces equivalent or far superior short channel performance compared to conventional UTSOI-FETs. Additionally, the above processing steps permit the use of lower halo doses as compared to conventional processes.Type: ApplicationFiled: May 25, 2007Publication date: November 27, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Omer H. Dokumaci, John M. Hergenrother, Shreesh Narasimha, Jeffrey W. Sleight
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Publication number: 20080206958Abstract: The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a Si-containing layer having a <110> crystal orientation and a biaxial compressive strain. The term “biaxial compressive stress” is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing <110> layer; and creating a biaxial strain in the silicon-containing <110> layer.Type: ApplicationFiled: May 6, 2008Publication date: August 28, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Victor Chan, Massimo V. Fischetti, John M. Hergenrother, Meikei Ieong, Rajesh Rengarajan, Alexander Reznicek, Paul M. Solomon, Chun-yung Sung, Min Yang
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Patent number: 7314790Abstract: The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a Si-containing layer having a <110> crystal orientation and a biaxial compressive strain. The term “biaxial compressive stress” is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing <110> layer; and creating a biaxial strain in the silicon-containing <110> layer.Type: GrantFiled: December 18, 2006Date of Patent: January 1, 2008Assignee: International Business Machines CorporationInventors: Victor Chan, Massimo V. Fischetti, John M. Hergenrother, Meikei Ieong, Rajesh Rengarajan, Alexander Reznicek, Paul M. Solomon, Chun-yung Sung, Min Yang
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Patent number: 7161169Abstract: The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a Si-containing layer having a <110> crystal orientation and a biaxial compressive strain. The term “biaxial compressive stress” is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing <110> layer; and creating a biaxial strain in the silicon-containing <110> layer.Type: GrantFiled: November 3, 2004Date of Patent: January 9, 2007Assignee: International Business Machines CorporationInventors: Victor Chan, Massimo V. Fischetti, John M. Hergenrother, Meikei Leong, Rajesh Rengarajan, Alexander Reznicek, Paul M. Solomon, Chun-yung Sung, Min Yang
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Patent number: 6518622Abstract: The present invention provides a VRG structure formed on a semiconductor wafer substrate. The VRG structure has a first source/drain region located in a semiconductor wafer substrate, and a conductive layer located adjacent the source/drain region, a second source/drain region and a conductive channel that extends from the first source/drain region to the second source/drain region. The conductive layer provides an electrical connection to the first source/drain region. The conductive layer may have a low sheet resistance that may be less than about 50 &OHgr;/square or less than about 20 &OHgr;/square, to the first source/drain region.Type: GrantFiled: March 20, 2000Date of Patent: February 11, 2003Assignee: Agere Systems Inc.Inventors: Hongzong Chew, Yih-Feng Chyan, John M. Hergenrother, Yi Ma, Donald P. Monroe
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Patent number: 6027975Abstract: A process for fabricating a vertical MOSFET device for use in integrated circuits is disclosed. In the process, at least three layers of material are formed sequentially on a semiconductor substrate. The three layers are arranged such that the second layer is interposed between the first and third layers. The second layer is sacrificial, that is, the layer is completely removed during subsequent processing. The thickness of the second layer defines the physical gate length of the vertical MOSFET. In the process the first and third layers have etch rates that are significantly lower than the etch rate of the second layer in an etchant selected to remove the second layer.After the at least three layers of material are formed on the substrate, a window or trench is formed in the layers. The window terminates at the surface of the silicon substrate in which one of either a source or drain region is formed in the silicon substrate. The window or trench is then filled with a semiconductor material.Type: GrantFiled: August 28, 1998Date of Patent: February 22, 2000Assignee: Lucent Technologies Inc.Inventors: John M. Hergenrother, Donald Paul Monroe