Abstract: Secondary battery protection circuits for protecting a battery from charging and/or discharging faults are provided. A secondary battery protection circuit may include a first terminal and a second terminal, a transistor electrically connected between the first terminal and the second terminal, a fuse electrically coupled to the gate of the transistor, and a fuse control circuit configured to cause current sufficient to open the fuse to pass through the fuse in the event of a fault condition.

Abstract: Secondary battery protection circuits for protecting a battery from charging and/or discharging faults are provided. A secondary battery protection circuit may include a first terminal and a second terminal, a transistor electrically connected between the first terminal and the second terminal, a fuse electrically coupled to the gate of the transistor, and a fuse control circuit configured to cause current sufficient to open the fuse to pass through the fuse in the event of a fault condition.

Abstract: A transient voltage suppressor may include a silicon controlled rectifier (SCR) having an anode coupled to Vcc. The SCR may include a PNP transistor (Q2) and an NPN transistor (Q3), the PNP transistor having a base in common with a collector of the NPN transistor and the PNP transistor having a collector in common with a base of the NPN transistor. The TVS may further include a Zener diode having an anode and cathode, wherein the anode is directly coupled to the base of the NPN transistor and/or the cathode is directly coupled to the base of the PNP transistor, and an additional NPN transistor (Q1). The cathode of the SCR may be directly coupled to a base of the additional NPN transistor, and a collector and emitter of the additional NPN transistor may be directly coupled in series between VCC and ground.

Abstract: A transient voltage suppressor may include a silicon controlled rectifier (SCR) having an anode coupled to Vcc. The SCR may include a PNP transistor (Q2) and an NPN transistor (Q3), the PNP transistor having a base in common with a collector of the NPN transistor and the PNP transistor having a collector in common with a base of the NPN transistor. The TVS may further include a Zener diode having an anode and cathode, wherein the anode is directly coupled to the base of the NPN transistor and/or the cathode is directly coupled to the base of the PNP transistor, and an additional NPN transistor (Q1). The cathode of the SCR may be directly coupled to a base of the additional NPN transistor, and a collector and emitter of the additional NPN transistor may be directly coupled in series between VCC and ground.

Abstract: A method for implementing an inductor-capacitor filter in an integrated circuit. Embodiments of the invention implement a 5-pole LC low-pass filter suitable for incorporation in wireless applications necessitating compact layouts. Inductors are formed in an IC as concentric coils on metallization layers, the concentric coils providing a negative coupling coefficient between the inductors. The invention provides programmable frequency response characteristics, enabling the transmission of high-frequency base band information while attenuating carrier RF frequencies.

Abstract: A CMOS integrated circuit is made compatible with TTL input signals. A regulator operates the CMOS gates in an array at a voltage that is slightly lower than the supply. The regulator sense circuit is made responsive to an operating gate and to a TTL bias reference. Accordingly, the regulator will compensate for changes in ambient conditions and manufacturing variations so that the gate array devices will reliably respond to TTL level switching signals.

Abstract: A CMOS integrated circuit power-on reset circuit has two cascaded threshold detectors for independently sensing the supply voltage attaining an amplitude sufficient to operate N and P-channel devices respectively and for providing a reset signal in response to the supply voltage meeting both conditions.

Abstract: The input of the Schmitt trigger is applied in parallel to the gates of a plurality of stacked MOS transistors. The stacked transistors are connected with their respective source and drain electrodes in series with a source of potential and with the drain electrode of a p channel transistor being connected to the adjacent drain electrode of an n channel transistor to define an output node on which the output hysteresis signal is derived. Upper and lower trip point reference potentials are established on the respective source electrodes of said output node defining p and n channel transistors. At least one of the trip point reference potentials is gated to the respective source electrode as a function of the state of the output, i.e., whether the output is high or low.