Abstract: A data processing system in which a plurality of processors or other memory access devices operate either synchronously or asynchronously with a memory interface device, which in turn provides access to one or more memory units on a time-division basis. This is accomplished by providing each memory unit a series of time-divisioned access opportunities and controlling the phase relationship between these time-divisioned access opportunities. Accordingly, two or more access devices can address an equal number of memory units simultaneously.

Abstract: A common communication controller is linked to a plurality of peripheral devices by a network interface bus. Packets containing information is communicated between the controller and the peripherals over the bus which consists of a parallel packet bus and a plurality of control lines utilized to implement a communication protocol which increases the efficiencies of packet communications by the utilization of additional direct command lines between the communications controller and peripherals.

Abstract: A hierarchical addressing technique is employed in a packet communications system to enhance flexibility in storing and referencing packet information. This method permits packet message data and certain packet control data to be stored in memory locations without having to be duplicated at a different memory location prior to transmission of the packet. This method is preferably employed in a ring configuration in which a series of packets have addressing mechanisms which points sequentially to each other to form a ring of packets received or to be transmitted.