Abstract: Switches and groups of IO ports may be divided into separate switch modules and IO modules that can be connected by high-speed low-loss management cables in a variety of configurations. Thereafter, the separate modules may be replaced independently of each other. The switch module may recognize, and thereafter ignore, unconnected ports, removing the performance penalty that sometimes arises when fewer than all available ports are connected. The switch module may rapidly adjust to addition, subtraction, and replacement of connected IO modules.

Abstract: Switches and groups of IO ports, conventionally integrated on a single shared PCB, may be divided into separate switch modules and IO modules that can be connected by high-speed low-loss management cables in a variety of configurations. Thereafter, the separate modules may be replaced independently of each other. Some of the management connections may be parallel, similar to production-data connections. Alternatively, a series of IO modules (e.g., a chain or a ring) may be managed by a single switch module using a management method. The management method may include collecting and updating configuration and status information specific to each of the IO modules and, by extension, each of their IO ports. This enables the switch module to recognize, and thereafter ignore, unconnected ports, removing the performance penalty that sometimes arises when fewer than all available ports are connected. It also allows the switch module to rapidly adjust to addition, subtraction, and replacement of connected IO modules.

Abstract: Examples disclosed herein relate to fabric cable emulation. Some examples disclosed herein include determining connection data associated with a connection between a fabric interface of a cluster node in a fabric cluster and a fabric switch. Based on the determined connection data, configuration parameters for the connection may be calculated and stored in a memory device on the cluster node. An interface signal may be asserted to the fabric interface of the cluster node after the calculated configuration parameters are stored to indicate that the cluster node is available in the fabric cluster.

Abstract: Examples disclosed herein relate to fabric cable emulation. Some examples disclosed herein include determining connection data associated with a connection between a fabric interface of a cluster node in a fabric cluster and a fabric switch. Based on the determined connection data, configuration parameters for the connection may be calculated and stored in a memory device on the cluster node. An interface signal may be asserted to the fabric interface of the cluster node after the calculated configuration parameters are stored to indicate that the cluster node is available in the fabric cluster.

Abstract: A queue based arbiter to arbitrate between N devices of a computer system for access to a system bus which eliminates the need to maintain a history of bus transactions by queuing bus requests to track when a bus request is posted. The arbiter provides fair access to the bus by maintaining a queue of requests that come in from each resource in the computer system. This is accomplished by continually sampling the individual request lines of the devices to determine if a device is requesting access to the bus. Each time the arbiter detects a request from a device it puts an entry representative of the specific device that has requested the bus into a queue that has at least N entries. Requests are granted in the order that they are queued.

Abstract: A method and apparatus for aliasing an address for a location in a memory system. The aliasing permits an address generating unit to access a memory block of variable size based upon an address space of fixed size so that the size of the memory block can be changed without changing the address generating software of the address generating unit. The invention provides an address aliasing device arranged to receive an address from the address generating unit. The address aliasing device includes a register that stores memory block size information. The memory block size information is read by the address aliasing device and decoded to provide bit information representative of the size of the memory block. The address aliasing device logically combines the bit information with appropriate corresponding bits of the input address to provide an alias address that is consistent with the size of the memory block.

Abstract: An apparatus and method for supplying an address and data to an external memory device. The number of pins available for supplying the address is less than the number of address lines required at the external memory device. A register is used to store the high order bits of the address and is pre-loaded with a default page value. An output of the register is coupled to an address input of the external memory. If the high order bits of the address are equal to the default page value, a control device couples the data lines directly to the external memory device and a read or write operation follows. If the two values are different, a paging cycle is performed where the high order address bits are latched through the register to the address input of the external memory and then the data bits are coupled to the external memory device.

Abstract: An access request prioritization and summary device for determining the current highest priority among n entities. The device includes a bitmap having n bit storage locations. Each one of the n bit storage locations corresponds to one of the entities and is used to store a value which represents when the corresponding entity is available for prioritization. A plurality of combinational logic blocks are connected to the bitmap so that each one of the combinational logic blocks receives a preselected portion of the values stored in the n bit storage locations of the bitmap. Each one of the combinational logic blocks has a token signal input and a token signal output. The token signal inputs and outputs are coupled together to form a series of token signal links between the combinational logic blocks.