Abstract: A method and apparatus for determining whether a TCP packet lands in-zone or out-of-zone of a TCP sequence space. An anchor representing the TCP sequence number of the last TCP data byte, plus one, is updated each time a TCP data packet is received. When a new TCP packet is received, the most significant bit, bit [31], is extracted from the anchor. A two-bit value is formed by adding 1 to the extracted bit. This two-bit value is pre-pended to bits [30:0] of the anchor, as bits [32:31], to produce a 33-bit test value. Then, the sequence number of the last TCP byte of the received packet is then compared to the anchor and the test value. If the sequence number is greater than or equal to the anchor, and less than the test value, the packet lands in-zone and may be processed normally.

Abstract: A method and apparatus for enqueuing and dequeuing packets to and from a shared packet memory, while avoiding collisions. An enqueue process or state machine enqueues packets for a communication connection (e.g., channel, queue pair, flow). A dequeue process or state machine operating in parallel dequeues packets and forwards them (e.g., to an InfiniBand node). Packets are stored in the shared packet memory, and status/control information is stored in a control memory that is updated for each packet enqueue and packet dequeue. Prior to updating the packet and/or control memory, each process interfaces with the other to determine if the other process is active and/or to identify the other process' current communication connection. If the enqueue process detects a collision, it pauses (e.g., for a predetermined number of clock cycles). If the dequeue process detects a collision, it selects a different communication connection to dequeue.

Abstract: A method and apparatus are provided for determining a suitable inter-packet gap (IPG), or a suitable extension to be added to a default IPG as a packet is processed. The apparatus includes an adder to add an incremental measure of a packet to an existing measure and produce a new measure (e.g., in bytes). The apparatus further includes a comparator which, if the new measure exceeds a programmable threshold (e.g., a stretch ratio), issues a signal to increase the IPG and decreases the new measure by the threshold. The current measure is then stored (e.g., in a register) for addition to the next incremental measure. A counter tracks the number of signals received before the end of the packet, at which time the total is forwarded to a component configured to insert or apply the IPG and the counter is reset for the next packet.

Abstract: A method and apparatus for enqueuing and dequeuing packets to and from a shared packet memory, while avoiding collisions. An enqueue process or state machine enqueues packets for a communication connection (e.g., channel, queue pair, flow). A dequeue process or state machine operating in parallel dequeues packets and forwards them (e.g., to an InfiniBand node). Packets are stored in the shared packet memory, and status/control information is stored in a control memory that is updated for each packet enqueue and packet dequeue. Prior to updating the packet and/or control memory, each process interfaces with the other to determine if the other process is active and/or to identify the other process' current communication connection. If the enqueue process detects a collision, it pauses (e.g., for a predetermined number of clock cycles). If the dequeue process detects a collision, it selects a different communication connection to dequeue.

Abstract: An apparatus and method for generating a cyclic redundancy code with multiple cyclic redundancy code circuits are disclosed. High throughput data protocols can work more robustly if accompanied by high throughput error checking to verify the integrity of the communicated data. One approach of improving the performance of cyclic redundancy code generation hardware that can save money and development time is to combine multiple cyclic redundancy code circuits to perform the error checking. Data received is processed across the multiple cyclic redundancy code circuits. Future cyclic redundancy code circuits can also be combined according to this approach.

Abstract: A method and apparatus are provided for determining a suitable inter-packet gap (IPG), or a suitable extension to be added to a default IPG as a packet is processed. The apparatus includes an adder to add an incremental measure of a packet to an existing measure and produce a new measure (e.g., in bytes). The apparatus further includes a comparator which, if the new measure exceeds a programmable threshold (e.g., a stretch ratio), issues a signal to increase the IPG and decreases the new measure by the threshold. The current measure is then stored (e.g., in a register) for addition to the next incremental measure. A counter tracks the number of signals received before the end of the packet, at which time the total is forwarded to a component configured to insert or apply the IPG and the counter is reset for the next packet.

Abstract: An apparatus and a method detect and automatically correct an illegal address in a peripheral connect interface bus addressing scheme. The value of a current bit is read. The value of a bit immediately left adjacent of the current bit is read. A value of 0 is outputted as the current bit in the event the value of the current bit is 1 and the value of the left adjacent bit is 0. In one specific embodiment, the apparatus employs a multiplexer and a single-bit register with a feedback as a one bit detection and correction circuit.

Abstract: A FIFO memory apparatus of the present invention includes an array of registers including a plurality of stacked subarrays. A first plurality of multiplexers is provided including one multiplexer for receiving data from each one of the subarrays. A second plurality of multiplexers is also provided each for receiving data from two other multiplexers. One of the second plurality of multiplexers supplies an output for the FIFO memory apparatus, while each of the others, in pairs, supply other multiplexers of the apparatus. The invention uses a four-way interleaved memory architecture for pre-decoding the FIFO read pointer and driving out data from one of the sixteen deep 32-bit wide registers, in advance. In this way, the final stage of the timing critical path is from the Q output of a toggle flip-flop to a two-to-one multiplexer and output buffer.

Abstract: A high modulus counter is provided for receiving a counter enable (CE) signal which switches between digital states. The counter is a single load conditional look ahead counter having a carry chain isolated from a timing critical path. The counter includes one toggle flip-flop for receiving the CE signal. The flip-flop has a first output and a second output. The first output and the second output are connected to an even counter and an odd counter, respectively. Both the output of the first counter and the output of the second counter are received by each of a plurality of multiplexers which are controlled by the first output of the toggle flip-flop. In this way, the high modulus counter outputs and increments the pointer signals of the odd counter and the even counter, alternatively. The even and odd internal counters are initially set at zero and one, respectively, and each increments by two. A second flip-flop may additionally receive the external CE signal for synchronization.

Abstract: An indicator structure including one or more lengths of perforated tubing arranged in a desired configuration, such as a traffic barricade. The tubing contains one or more flash lamps which produce a light-tunnel effect during operation to provide a high intensity warning or indicating signal in a pre-selected configuration of flash illumination via the tubing perforations.

Abstract: A cold cathode arc discharge flash lamp has a cathode assembly in which an electron emissive pellet is secured on the lead wire or rod entering the flash tube envelope. One or more coils of molybdenum or a similar body of ceramic refractory shield the emissive face of the pellet from destructive ion bombardment while exposing the face for electron emission.