Patents by Inventor John M. McKenna
John M. McKenna has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9964516Abstract: An ISFET includes a control gate coupled to a floating gate in a CMOS device. The control gate, for example, a poly-to-well capacitor, is configured to receive a bias voltage and effect movement of a trapped charge between the control gate and the floating gate. The threshold voltage of the ISFET can therefore by trimmed to a predetermined value, thereby storing the trim information (the amount of trapped charge in the floating gate) within the ISFET itself.Type: GrantFiled: February 8, 2017Date of Patent: May 8, 2018Assignee: NXP USA, INC.Inventors: Patrice M. Parris, Weize Chen, Richard J. De Souza, Md M. Hoque, John M. McKenna
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Publication number: 20170146485Abstract: An ISFET includes a control gate coupled to a floating gate in a CMOS device. The control gate, for example, a poly-to-well capacitor, is configured to receive a bias voltage and effect movement of a trapped charge between the control gate and the floating gate. The threshold voltage of the ISFET can therefore by trimmed to a predetermined value, thereby storing the trim information (the amount of trapped charge in the floating gate) within the ISFET itself.Type: ApplicationFiled: February 8, 2017Publication date: May 25, 2017Inventors: Patrice M. Parris, Weize Chen, Richard J. De Souza, Md M. Hoque, John M. McKenna
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Patent number: 9599587Abstract: An ISFET includes a control gate coupled to a floating gate in a CMOS device. The control gate, for example, a poly-to-well capacitor, is configured to receive a bias voltage and effect movement of a trapped charge between the control gate and the floating gate. The threshold voltage of the ISFET can therefore by trimmed to a predetermined value, thereby storing the trim information (the amount of trapped charge in the floating gate) within the ISFET itself.Type: GrantFiled: September 5, 2014Date of Patent: March 21, 2017Assignee: NXP USA, INC.Inventors: Patrice M. Parris, Weize Chen, Richard J. De Souza, Md M. Hoque, John M. McKenna
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Publication number: 20140375370Abstract: An ISFET includes a control gate coupled to a floating gate in a CMOS device. The control gate, for example, a poly-to-well capacitor, is configured to receive a bias voltage and effect movement of a trapped charge between the control gate and the floating gate. The threshold voltage of the ISFET can therefore by trimmed to a predetermined value, thereby storing the trim information (the amount of trapped charge in the floating gate) within the ISFET itself.Type: ApplicationFiled: September 5, 2014Publication date: December 25, 2014Inventors: PATRICE M. PARRIS, WEIZE CHEN, RICHARD J. DE SOUZA, MD M. HOQUE, JOHN M. MCKENNA
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Patent number: 8878257Abstract: An ISFET includes a control gate coupled to a floating gate in a CMOS device. The control gate, for example, a poly-to-well capacitor, is configured to receive a bias voltage and effect movement of a trapped charge between the control gate and the floating gate. The threshold voltage of the ISFET can therefore by trimmed to a predetermined value, thereby storing the trim information (the amount of trapped charge in the floating gate) within the ISFET itself.Type: GrantFiled: June 4, 2010Date of Patent: November 4, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Patrice M. Parris, Weize Chen, Richard J. De Souza, Md M. Hoque, John M. McKenna
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Publication number: 20110299337Abstract: An ISFET includes a control gate coupled to a floating gate in a CMOS device. The control gate, for example, a poly-to-well capacitor, is configured to receive a bias voltage and effect movement of a trapped charge between the control gate and the floating gate. The threshold voltage of the ISFET can therefore by trimmed to a predetermined value, thereby storing the trim information (the amount of trapped charge in the floating gate) within the ISFET itself.Type: ApplicationFiled: June 4, 2010Publication date: December 8, 2011Applicant: Freescale Semiconductor, Inc.Inventors: Patrice M. Parris, Weize Chen, Richard J. De Souza, Md M. Hoque, John M. McKenna
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Patent number: 7700996Abstract: A tunable antifuse element (102, 202, 204, 504, 952) includes a substrate material (101) having an active area (106) formed in a surface, a gate electrode (104) having at least a portion positioned above the active area (106), and a dielectric layer (110) disposed between the gate electrode (104) and the active area (106). The dielectric layer (110) includes a tunable stepped structure (127). During operation, a voltage applied between the gate electrode (104) and the active area (106) creates a current path through the dielectric layer (110) and a rupture of the dielectric layer (110) in a rupture region (130). The dielectric layer (110) is tunable by varying the stepped layer thicknesses and the geometry of the layer.Type: GrantFiled: January 29, 2009Date of Patent: April 20, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Patrice M. Parris, Weize Chen, John M. McKenna, Jennifer H. Morrison, Moaniss Zitouni, Richard J. De Souza
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Publication number: 20090127587Abstract: A tunable antifuse element (102, 202, 204, 504, 952) includes a substrate material (101) having an active area (106) formed in a surface, a gate electrode (104) having at least a portion positioned above the active area (106), and a dielectric layer (110) disposed between the gate electrode (104) and the active area (106). The dielectric layer (110) includes a tunable stepped structure (127). During operation, a voltage applied between the gate electrode (104) and the active area (106) creates a current path through the dielectric layer (110) and a rupture of the dielectric layer (110) in a rupture region (130). The dielectric layer (110) is tunable by varying the stepped layer thicknesses and the geometry of the layer.Type: ApplicationFiled: January 29, 2009Publication date: May 21, 2009Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Patrice M. Parris, Weize Chen, John M. McKenna, Jennifer H. Morrison, Moaniss Zitouni, Richard J. De Souza
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Patent number: 7528015Abstract: A tunable antifuse element (102, 202, 204, 504, 952) and method of fabricating the tunable antifuse element, including a substrate material (101) having an active area (106) formed in a surface, a gate electrode (104) having at least a portion positioned above the active area (106), and a dielectric layer (110) disposed between the gate electrode (104) and the active area (106). The dielectric layer (110) including the fabrication of one of a tunable stepped structure (127). During operation, a voltage applied between the gate electrode (104) and the active area (106) creates a current path through the dielectric layer (110) and a rupture of the dielectric layer (110) in a plurality of rupture regions (130). The dielectric layer (110) is tunable by varying the stepped layer thicknesses and the geometry of the layer.Type: GrantFiled: June 28, 2005Date of Patent: May 5, 2009Assignee: Freescale Semiconductor, Inc.Inventors: Patrice M. Parris, Weize Chen, John M. McKenna, Jennifer H. Morrison, Moaniss Zitouni, Richard J. De Souza
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Patent number: 5385445Abstract: A multi-stage open impeller centrifugal pump, primarily used for charging service. The pump uses multivane, 27 vanes, impellers, mounted on a single shaft. Rotor parts are a loose fit to the pump shaft and channel rings are pulled together with bolts. Jackbolts are used to separate the channel rings. A channel ring bushing is provided with a loose fit. The channel ring bushing is axially and radially retained by the channel ring and diffusor.Type: GrantFiled: December 3, 1993Date of Patent: January 31, 1995Assignee: Ingersoll-Dresser Pump CompanyInventor: John M. McKenna
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Patent number: 5320489Abstract: A radial diffuser for a centrifugal pump. The diffuser has a plurality of diffusing passages wherein the width of the diffusing passage is constant and the cross-sectional area of the diffusing passage increases from the inlet of the diffusing passage to the outlet of the diffusing passage. This type of diffuser has a reduced outer diameter relative to prior art diffusers.Type: GrantFiled: June 1, 1993Date of Patent: June 14, 1994Assignee: Ingersoll-Dresser Pump CompanyInventor: John M. McKenna
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Patent number: 5299813Abstract: A floating seal ring is disposed within a retainer ring encircling a shaft which extends through the retainer ring. The seal ring is permitted to float radially with respect to the shaft but is retained axially with respect to the shaft. A pin protrudes from the seal ring into a bore in the retainer ring to preclude rotational movement of the seal ring relative to the shaft. The seal ring has an inner diameter which is greater at one end thereof than at the other end thereof so that fluid flow through an annular clearance between the seal ring and the shaft is accelerated. In one embodiment, the seal ring has an annular inner surface that is tapered. In another embodiment, the seal ring has an annular inner surface that is stepped.Type: GrantFiled: October 23, 1992Date of Patent: April 5, 1994Assignee: Ingersoll-Dresser Pump CompanyInventor: John M. McKenna
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Patent number: 4971459Abstract: A bearing arrangement wherein a shaft of uniform diameter is supported in a journal bearing having multiple sections located axially along said shaft at different locations. Each journal bearing section includes a circular journal bore receiving the shaft with the axis of said journal bores being parallel and displaced relative to each other and to the axis of the enclosed shaft in a plane normal to the axis of the shaft.Type: GrantFiled: March 23, 1990Date of Patent: November 20, 1990Assignee: Ingersoll-Rand CompanyInventor: John M. McKenna
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Patent number: D357030Type: GrantFiled: December 2, 1993Date of Patent: April 4, 1995Assignee: Ingersoll-Dresser Pump CompanyInventor: John M. McKenna