Abstract: A method and system for accessing image data in a plurality of different color formats. The image data are stored in a system memory (120) in one of the color formats. The method and system enable an access or request to load image data in a different color format from an address in a color conversion address space, which comprises an alternate memory space. Pixel color data in the color conversion address space have a corresponding address for data in the other color format that is stored in system memory. The corresponding address is determined by subtracting a predefined offset from the conversion memory address. Differences in the size of the color format data for the requested pixels are accommodated by applying an appropriate factor to determine the system memory address.

Abstract: A method and system for producing a composite image of two or more graphic objects. In a set top box (44) designed to be used with a television receiver or video monitor (40), an application specific integrated circuit (ASIC) (76) is provided that includes a dynamic composition engine (DCE) (84), which generates a composite image for display on the screen of the television receiver. The composite image is based upon Screen Descriptor data that include a Line Descriptor defining each scan line using Span Descriptors. A Span Descriptor defines the portion of a line occupied by one of the objects that will comprise the composite image and specifies how that object will be combined with other objects on the line. A line buffer is filled with the pixels for the scan line next to be displayed while data in a second line buffer are written to the display screen.

Abstract: A peripheral device interrupt controller maintains a count of pending interrupt events for a peripheral device up to a preset limit and times a preset delay interval from a first pending interrupt event or last interrupt servicing before asserting an interrupt request. When the interrupt request is asserted, the then pending interrupt events can be serviced as a group by a central processing unit of a computer. The overhead of processing a separate interrupt request for each interrupt event is thus avoided. The preset limit and preset delay interval can be set under software control to control the rate at which interrupt requests can be asserted by the peripheral device.

Abstract: A cache coherency protocol for a multi-processor system which provides for read/write, read-only and transitional data states and for an indication of these states to be stored in a memory directory in main memory. The transitional data state occurs when a processor requests from main memory a data block in another processor's cache and the request is pending completion. All subsequent read requests for the data block during the pendency of the first request are inhibited until completion of the first request. Also provided in the memory directory for each data block is a field for identifying the processor which owns the data block in question. Data block ownership information is used to determine where requested owned data is located.