Abstract: A pattern recognizer uses the method of n-tuples applied to a matrix containing (e.g.) features derived from input speech. A template store records during a training sequence the frequencies of occurrence of combinations of bits with each n-tuple group. During recognition frequencies associated with combinations which occur are used to form a measure of similarity.

Abstract: A stereo coding system is described in which 7 kHZ bandwidth sum (L+R) and difference (L-R) signals are converted to digital form (11 and 12). The difference signal is then bandlimited (13) to 2 kHZ and downsampled (14) to 4K samples/sec prior to being encoded (16), and the sum signal is encoded (15); both are then multiplexed together (17) prior to transmission. After reception, the signal is demultiplexed (19) and the difference signal is decoded (20) upsampled (21) to its original bit rate and filtered to prevent aliasing (22), and the sum signal is delayed in a digital buffer (28) and decoded (24) prior to both being converted back to analogue form (23 and 25). The delay introduced by the digital buffer (28) equalizes the excess delay introduced into the difference signal.

Abstract: Second and third-order RC active filter sections are described both based on a similar basic twin-tee network. The circuits include a single operational amplifier and are such that the poles and zeros of the network can be adjusted with little interaction by varying resistances in sequence. It is possible to construct the sections using capacitors of wide tolerance.

Abstract: An equalizer network that exhibits stability and may be cascaded with a transmission channel is disclosed. The network includes only two operational amplifiers, resistors and capacitors and provides a bump shaped amplitude characteristic at resonance frequency. The equalizer may be modified to exhibit selectively a `bump` or `dip` at resonance, and may be so constructed that trimming operations and the independent selection of parameters is facilitated.

Abstract: An unconditionally stable gyrator circuit includes two interconnected d.c. differential amplifiers. The terminals of an input port are respectively connected to the non-inverting inputs of the amplifiers, that to the second amplifier being connected through a resistor. The inverting input of the first amplifier is connected to the non-inverting input of the second, the output of the first amplifier is connected through a resistor to the inverting input of the second amplifier and the output of the second amplifier is connected through a resistor to the non-inverting input of the first amplifier. Two alternative output ports are provided between the output of the first amplifier and the non-inverting input of the second, and between the output of the second amplifier and its inverting input. The output port which is not used has a resistive impedance connected across it.