Patents by Inventor John M. Thendean
John M. Thendean has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10673438Abstract: A digital signal processor (DSP) slice is disclosed. The DSP slice includes an input stage to receive a plurality of input signals, a pre-adder coupled to the input stage and configured to perform one or more operations on one or more of the plurality of input signals, and a multiplier coupled to the input stage and the pre-adder and configured to perform one or more multiplication operations on one or more of the plurality of input signals or the output of the pre-adder. The DSP slice further includes an arithmetic logic unit (ALU) coupled to the input stage, the pre-adder, and the multiplier. The ALU is configured to perform one or more mathematical or logical operations on one or more of the plurality of input signals, the output of the pre-adder, or the output of the multiplier.Type: GrantFiled: April 2, 2019Date of Patent: June 2, 2020Assignee: XILINX, INC.Inventors: Adam Elkins, Ephrem C. Wu, John M. Thendean, Adnan Pratama, Yashodhara Parulkar, Xiaoqian Zhang
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Patent number: 9081634Abstract: An apparatus is disclosed. This apparatus includes a digital signal processing (“DSP”) block having a preadder-register block coupled to receive first through fourth input operands. A multiplier is coupled to the preadder-register block to receive a multiplicand operand and a multiplier operand. A first register block is coupled to the multiplier to receive sets of partial products from the multiplier. A second register block coupled to receive the third operand input. An arithmetic logic unit (“ALU”) block is coupled to the pre-adder-register block, the first register block and the second register block. The ALU block includes four input multiplexers and an ALU, where the ALU is coupled to receive outputs from each of the four input multiplexers.Type: GrantFiled: November 9, 2012Date of Patent: July 14, 2015Assignee: XILINX, INC.Inventors: James M. Simkins, Wayne E. Wennekamp, John M. Thendean, Adam Elkins, Richard L. Walke
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Patent number: 8543635Abstract: A digital signal processing block with a preadder stage for an integrated circuit is described. The digital signal processing block includes a preadder stage and a control bus. The control bus is coupled to the preadder stage for dynamically controlling operation of the preadder stage. The preadder stage includes: a first input port of a first multiplexer coupled to the control bus; a second input port of a first logic gate coupled to the control bus; a third input port of a second logic gate coupled to the control bus; and a fourth input port of an adder/subtractor coupled to the control bus.Type: GrantFiled: January 27, 2009Date of Patent: September 24, 2013Assignee: Xilinx, Inc.Inventors: James M. Simkins, Alvin Y. Ching, John M. Thendean, Vasisht M. Vadi, Chi Fung Poon, Muhammad Asim Rab
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Patent number: 7882165Abstract: A digital signal processing circuit including: a multiplier circuit; a plurality of multiplexers coupled to the multiplier circuit and controlled by a first opcode; and an arithmetic logic unit coupled to plurality of multiplexers and controlled by a second opcode.Type: GrantFiled: April 21, 2006Date of Patent: February 1, 2011Assignee: Xilinx, Inc.Inventors: James M. Simkins, Jennifer Wong, Bernard J. New, Alvin Y. Ching, John M. Thendean, Anna Wing Wah Wong, Vasisht Mantra Vadi, David P. Schultz
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Patent number: 7870182Abstract: An integrated circuit having a digital signal processing (DSP) circuit is disclosed. The DSP circuit includes: a plurality of multiplexers receiving a first set, second set, and third set of input data bits, where the plurality of multiplexers are coupled to a first opcode register; a bitwise adder coupled to the plurality of multiplexers for generating a sum set of bits and a carry set of bits from bitwise adding together the first, second, and third set of input data bits; and a second adder coupled to the bitwise adder for adding together the sum set of bits and carry set of bits to produce a summation set of bits and a plurality of carry-out bits, where the second adder is coupled to a second opcode register.Type: GrantFiled: May 12, 2006Date of Patent: January 11, 2011Assignee: Xilinx Inc.Inventors: John M. Thendean, Jennifer Wong, Bernard J. New, Alvin Y. Ching, James M. Simkins, Anna Wing Wah Wong, Vasisht Mantra Vadi
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Patent number: 7865542Abstract: A digital signal processing block having: 1) a first digital signal processing element including: a first multiplexer of a first plurality of multiplexers, the first multiplexer selecting between a first data input and a first zero constant input; and a first arithmetic unit coupled to the first plurality of multiplexers, the first arithmetic logic unit configured for addition; and 2) a second digital signal processing element including: a second multiplexer of a second plurality of multiplexers, the second multiplexer selecting between a second data input and a second zero constant input; and a second arithmetic unit coupled to the second plurality of multiplexers and to a third multiplexer of the first plurality of multiplexers, the second arithmetic unit configured for addition.Type: GrantFiled: May 12, 2006Date of Patent: January 4, 2011Assignee: Xilinx, Inc.Inventors: Bernard J. New, Vasisht Mantra Vadi, Jennifer Wong, Alvin Y. Ching, John M. Thendean, Anna Wing Wah Wong, James M. Simkins
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Patent number: 7860915Abstract: A method for detecting a pattern from an arithmetic logic unit (ALU) in an integrated circuit. The method includes the steps of: generating an output from an ALU; bitwise comparing the ALU output to a pattern to produce a first output; inverting the pattern and comparing the ALU output with the inverted pattern to produce a second output; bitwise masking the first and second outputs using a mask of a plurality of masks to produce third and fourth output bits; combining the third and fourth output bits to produce first and a second output comparison bits; and storing the first and second output comparison bits in a memory.Type: GrantFiled: May 12, 2006Date of Patent: December 28, 2010Assignee: Xilinx, Inc.Inventors: Vasisht Mantra Vadi, Jennifer Wong, Bernard J. New, Alvin Y. Ching, John M. Thendean, Anna Wing Wah Wong, James M. Simkins
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Patent number: 7853632Abstract: A physical floorplan for a digital signal processing (DSP) block including; an interconnect column having a plurality of programmable interconnect elements; a first DSP element having a plurality of first columns, a first output register column of the plurality of first columns positioned adjacent to the interconnect column; and a second DSP element, having a plurality of second columns a second output register column of the plurality of second columns positioned adjacent to the interconnect column.Type: GrantFiled: May 12, 2006Date of Patent: December 14, 2010Assignee: Xilinx, Inc.Inventors: Alvin Y. Ching, Jennifer Wong, Bernard J. New, James M. Simkins, John M. Thendean, Anna Wing Wah Wong, Vasisht Mantra Vadi
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Patent number: 7853634Abstract: An Integrated Circuit (IC) having a single-instruction-multiple-data (SIMD) is disclosed. The SIMD circuit includes: a plurality of multiplexers controlled by a first opcode; and an arithmetic logic unit (ALU) coupled to the plurality of multiplexers and controlled by a second opcode; and wherein the ALU has a plurality of adders, where the plurality of adders are controlled by some bits of the second opcode, and where a first adder of the plurality of adders adds a plurality of input bits to produce first summation bits and a first carry bit; the first adder operating concurrently with the other adders of the plurality of adders.Type: GrantFiled: May 12, 2006Date of Patent: December 14, 2010Assignee: Xilinx, Inc.Inventors: James M. Simkins, Jennifer Wong, Bernard J. New, Alvin Y. Ching, John M. Thendean, Anna Wing Wah Wong, Vasisht Mantra Vadi
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Patent number: 7853636Abstract: An integrated circuit (IC) for convergent rounding including: an adder circuit configured to produce a summation; a comparison circuit configured to bitwise compare the summation with an input pattern, bitwise mask the comparison using a mask, and combine the masked comparison to produce a comparison bit; and rounding circuitry for rounding the summation based at least in part on the comparison bit.Type: GrantFiled: May 12, 2006Date of Patent: December 14, 2010Assignee: Xilinx, Inc.Inventors: Bernard J. New, Jennifer Wong, James M. Simkins, Alvin Y. Ching, John M. Thendean, Anna Wing Wah Wong, Vasisht Mantra Vadi
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Patent number: 7849119Abstract: An integrated circuit for pattern detection including: an arithmetic logic unit coupled to a comparison circuit, where the arithmetic logic unit is programmed by an opcode; a selected pattern of a plurality of patterns selected by a first multiplexer, where the first multiplexer is coupled to the comparison circuit; and a register coupled to the comparison circuit for storing at least a partial comparison between an output of the arithmetic logic unit and the selected pattern.Type: GrantFiled: May 12, 2006Date of Patent: December 7, 2010Assignee: Xilinx, Inc.Inventors: Vasisht Mantra Vadi, Jennifer Wong, Bernard J. New, Alvin Y. Ching, John M. Thendean, Anna Wing Wah Wong, James M. Simkins
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Patent number: 7844653Abstract: A digital signal processing circuit having a pre-adder circuit includes; a first register block and a pre-adder circuit coupled to a multiplier circuit and to a set of multiplexers, where the set of multiplexers are controlled by an opcode, and where the pre-adder circuit has a first adder circuit; and an arithmetic logic unit (ALU) having a second adder circuit and coupled to the set of multiplexers.Type: GrantFiled: May 12, 2006Date of Patent: November 30, 2010Assignee: Xilinx, Inc.Inventors: James M. Simkins, John M. Thendean, Vasisht Mantra Vadi, Bernard J. New, Jennifer Wong, Anna Wing Wah Wong, Alvin Y. Ching
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Patent number: 7840630Abstract: An Arithmetic Logic Unit that includes first multiplexers coupled to a first adder, the first multiplexers controlled by a first opcode register; second multiplexers receiving input from the first adder and coupled to a second adder; and a second opcode register for controlling one or more of the second multiplexers, the first adder, or the second adder. A combination of the bits in the first and second opcode registers configures the ALU to perform one or more arithmetic operations or one or more logic operations or any combination thereof.Type: GrantFiled: May 12, 2006Date of Patent: November 23, 2010Assignee: XILINX, Inc.Inventors: Anna Wing Wah Wong, Jennifer Wong, Bernard J. New, Alvin Y. Ching, John M. Thendean, James M. Simkins, Vasisht Mantra Vadi, David P. Schultz
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Patent number: 7840627Abstract: An integrated circuit that includes a digital signal processing element (DSPE) having a first and a second register block coupled to a first arithmetic logic unit (ALU) circuit; a middle DSPE adjacent to the top DSPE having a third and a fourth register block coupled to a second ALU circuit, where the third register block is coupled to the first register block, and the fourth register block register block is coupled to the second register block; and a bottom DSPE adjacent to the middle DSPE having a fifth and a sixth register block coupled to a third ALU circuit, where the fifth register block is coupled to the third register block and the sixth register block register block is coupled to the fourth register block.Type: GrantFiled: May 12, 2006Date of Patent: November 23, 2010Assignee: Xilinx, Inc.Inventors: James M. Simkins, Jennifer Wong, Bernard J. New, Alvin Y. Ching, John M. Thendean, Anna Wing Wah Wong, Vasisht Mantra Vadi
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Publication number: 20100191786Abstract: A digital signal processing block with a preadder stage for an integrated circuit is described. The digital signal processing block includes a preadder stage and a control bus. The control bus is coupled to the preadder stage for dynamically controlling operation of the preadder stage. The preadder stage includes: a first input port of a first multiplexer coupled to the control bus; a second input port of a first logic gate coupled to the control bus; a third input port of a second logic gate coupled to the control bus; and a fourth input port of an adder/subtractor coupled to the control bus.Type: ApplicationFiled: January 27, 2009Publication date: July 29, 2010Applicant: XILINX, INC.Inventors: James M. Simkins, Alvin Y. Ching, John M. Thendean, Vasisht M. Vadi, Chi Fung Poon, Muhammad Asim Rab
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Patent number: 6981153Abstract: It is sometimes desirable to protect a design used in a PLD from being copied. If the design is stored in a different device from the PLD and read into the PLD through a bitstream, the design may be encrypted as it is read into the PLD and decrypted within the PLD before being loaded into configuration memory cells for configuring the PLD. According to the invention, in such a device, a method is provided to prevent the design from being read back from the PLD in its decrypted state if it had been encrypted when loaded into the PLD.Type: GrantFiled: November 28, 2000Date of Patent: December 27, 2005Assignee: Xilinx, Inc.Inventors: Raymond C. Pang, Walter N. Sze, John M. Thendean, Stephen M. Trimberger, Jennifer Wong
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Patent number: 6965675Abstract: It is sometimes desirable to encrypt a design for loading into a PLD so that an attacker may not learn and copy the design as it is being written into the PLD. It is desirable that decryption keys be stored within the PLD, and that they be loaded conveniently before a board including the PLD is sold. The invention allows the PLD to be placed into a printed circuit board and the board to be tested using a JTAG port of the PLD, and then allows the decryption keys to be loaded into a key memory using the JTAG port. Loading of the keys can be performed without also loading of a design into the PLD. Loading may be performed without the use of a device programmer.Type: GrantFiled: November 28, 2000Date of Patent: November 15, 2005Assignee: Xilinx, Inc.Inventors: Stephen M. Trimberger, Raymond C. Pang, John M. Thendean
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Patent number: 6931543Abstract: To prevent copying of a design implemented in a programmable logic device (PLD), the PLD itself stores a decryption key or keys loaded by the designer, and includes a decryptor for decrypting an encrypted configuration bitstream as it is loaded into the PLD. The PLD also includes logic for reading header information that indicates whether the bitstream is encrypted, and can accept both encrypted and unencrypted bitstreams. The encryption keys may be stored in non-volatile memory or backed up with a battery so that they are retained when power is removed.Type: GrantFiled: November 28, 2000Date of Patent: August 16, 2005Assignee: Xilinx, Inc.Inventors: Raymond C. Pang, Walter N. Sze, Jennifer Wong, Stephen M. Trimberger, John M. Thendean, Kameswara K. Rao