Abstract: A high speed low power digital-to-analog (D/A) converter (DAC) includes a plurality of least significant bit (LSB) cells that collectively define a total output of the DAC. Each LSB cell includes a differential current driver that has reduced capacitive loading due to a cascode structure of the current driver wherein transistors are biased to desired levels and current sources are switched on and off to control the differential output signal.

Abstract: A high speed digital-to-analog (D/A) converter (DAC) includes a plurality of least significant bit (LSB) cells that collectively define a total output of the DAC. Each LSB cell includes a differential current driver that has reduced capacitive loading due to a cascode structure of the current driver wherein transistors are biased to desired levels and current sources are switched on and off to control the differential output signal.

Abstract: An improved AUI (CI) line driver that implements three modes: an active mode, an idle mode, and a reverse mode. The reverse mode allows use of the AUI line driver cell in a reversible AUI, that is, in an AUI that can be reconfigured for controller mode, or transceiver mode. The controller mode AUI has two AUI receivers and an AUI driver, while the transceiver mode has two AUI drivers and an AUI receiver. Having one driver cell (the CI cell) that can be reversed permits reconfiguring the AUI into either mode.

Abstract: An apparatus and method for a transition detector and pulse width qualifying circuit for a differential receiver. The circuit generates pulses at every transition of a differential input signal and asserts a time-out signal upon detection of an end-of-transmission delimiter pulse. The circuit also detects true or inverted linkpulses.

Abstract: An integrated media attachment unit (MAU) operative for interfacing Digital Terminal Equipment (DTE) on a Local Area Network (LAN) using twisted pair media. The twisted pair function as either a DTE MAU or a repeater MAU. A line driver for the twisted pair differential signal provides a ramped response with low jitter while an improved Attachment Unit Interface (AUI) driver uses CMOS technology and provides simplified End-of-Transmission Delimiter (ETD) control. The twisted pair MAU includes a combined override and status indication of link status and an additional feature to allow automatic polarity reversal of differential signal input lines and polarity status signalling.

Abstract: A bi-phase decoder for extraction of an embedded clock in a Manchester encoded signal operating at about ten megahertz. A phase-lock loop (PLL) includes a phase frequency detector and an interruptible voltage controlled oscillator (VCO). The PLL has a narrow bandwidth for stability to reduce effects of five megahertz components on clock extraction. The bi-phase decoder has a fast acquisition time to ensure frequency and phase lock during a preamble portion of an input data packet. A clock reference operates the PLL and the VCO at a nominal frequency of the embedded clock. Receipt of a data packet initiates interruption of the VCO operation to switch in the received data. The VCO resumes operation in phase with the received data packet and at about the proper frequency, therefore acquisition is fast. The VCO is designed to resume operation after operation at a particular phase to help in phase alignment.

Abstract: An integrated media attachment unit (MAU) operative for interfacing Digital Terminal Equipment (DTE) on a Local Area Network (LAN) using twisted pair media. The twisted pair function as either a DTE MAU or a repeater MAU. A line driver for the twisted pair differential signal provides a ramped response with low jitter while an improved Attachment Unit Interface (AUI) driver uses CMOS technology and provides simplified End-of-Transmission Delimiter (ETD) control. The twisted pair MAU includes a combined override and status indication of link status and an additional feature to allow automatic polarity reversal of differential signal input lines and polarity status signalling.

Abstract: A differential receiver incorporated into a MAU which receives both Manchester packets and linkpulses according to the IEEE 802.3 10Base-T standard has polarity detection and correction circuit for automatically detecting a reversed polarity for RD input lines. The differential receiver samples incoming pulses for time, amplitude and pulse width qualification and makes a preliminary polarity determination based upon polarity of such qualified pulses. This preliminary polarity allows a linktest state machine to transition to a link.sub.-- pass state, enabling output drivers of the MAU. Additionally, the linkpulse polarity information initially makes a polarity determination for the entire differential receiver which asserts a FIX POLARITY signal. The FIX POLARITY signal controls a correction circuit which internally remedies reversed input lines. Preferably, the correction circuit internally reroutes the signals.

Abstract: An integrated media attachment unit (MAU) operative for interfacing Digital Terminal Equipment (DTE) on a Local Area Network (LAN) using twisted pair media. The twisted pair function as either a DTE MAU or a repeater MAU. A line driver for the twisted pair differential signal provides a ramped response with low jitter while an improved Attachment Unit Interface (AUI) driver uses CMOS technology and provides simplified End-of-Transmission Delimiter (EDT) control. The twisted pair MAU includes a combined override and status indication of link status and an additional feature to allow automatic polarity reversal of differential signal input lines and polarity status signalling.

Abstract: A digital-to-analog converter for converting a digital signal having a plurality of binary bits into an analog output signal includes an R-2R ladder network forming a plurality of switching cells corresponding in number to the number of the binary bits. Each switching cell is formed of first, second and third pairs of CMOS transistors defining cross resistances of the ladder network and of a fourth pair of CMOS transistors defining a series resistance of ladder network. A pair of differential circuits drives each switching cell to control switching symmetry and conversion speed.

Abstract: An MOS sampling comparator circuit including a differential amplifier for producing first and second amplified signals, a first positive feedback circuit for further amplifying the first amplified signal, a second positive feedback circuit for further amplifying the second amplified signal, a strobed latch, having a positive feedback circuit, for further amplifying and storing the signals from the first and second positive feedback circuits, and a circuit for outputting complementary logic signals in response to the latched signals. By providing the first and second positive feedback circuits, small analog differential voltage input signals to the differential amplifier are further amplified and coupled without delay to the latch, resulting in an accurate conversion of the analog input signals to logic signals at high speed.