Abstract: A transfer metal configuration and fabrication process possessing increased probability of intersecting a transverse metallization level are presented, without employing an increase in actual metal thickness. The transfer metal is configured with a non-rectangular transverse cross-section such that the thickness of the electrical connect remains the same, but the transverse contact area of the exposed metal is increased. The entire transfer metal may have the same transverse cross-sectional configuration or have portions with different transverse configurations. If different configurations are employed, each portion of the transfer metal to be transversely intersected has the enhanced cross-sectional configuration. A tiered transverse configuration is presented which facilitates electrical connection of the transfer metal to a metal level on a face of a semiconductor cube structure.

Abstract: A process is provided for fabricating a semiconductor structure wherein the structure has to be exposed to certain oxidizing conditions during certain of its processing steps, such as its high temperature annealing in an oxidizing ambient. It includes depositing a "sacrificial" layer, such as silicon, to provide a uniformly oxidizing surface during subsequent annealing operations. This sacrificial layer, which oxidizes uniformly, produces an oxide layer which also etches uniformly. Thus, after the annealing is completed, the surface oxide is removed through etching and the sacrificial layer is then also removed through a different etching step.

Abstract: A simple process is provided which forms a bulk CMOS structure by depositing a layer of material which resists oxidation, e.g., a barrier layer of silicon nitride on an N- semiconductor substrate, forming a P well in the substrate through a given segment of the barrier layer, removing a first segment of the barrier layer to form N+ regions for N channel source and drain and N- substrate contact, removing a second segment of the barrier layer to form a P+ field region, removing a third segment of the barrier layer to form P+ regions for source and drain of a P channel device, forming a first control electrode having a given work function for the P channel device which acts as an ion barrier and then forming a second control electrode between the N channel source and drain regions having a work function different from that of the first control electrode.